We predict the performance gap between the n- and p-type WZ-InSb nanowires (NWs) with gate-all-around (GAA) configuration for the complementary metal oxide semiconductor (CMOS) field-effect transistors (FETs) at the sub-1 nm nanowire diameter (DNW) at the gate length (Lg) of sub-5 nm, simulated for the first time by using an accurate ab initio quantum transport simulation technique. Bulk indium antimony (InSb) has nearly 55 times higher electron mobility \({\mu }_{\text{e}}\) than silicon but suffers from a much lower hole mobility \({\mu }_{\text{h}}\) ( \({\mu }_{\text{e}}\) / \({\mu }_{\text{h}}\) = 90), thus unsuited to CMOS application with a single material. In the sub-1 nm DNW, the light hole and heavy hole band inversion has diminished the performance gap of the n-type and p-type WZ-InSb NW MOSFETs. Excellent gate scaling performance is achieved at Lg = 3 nm, with on-state current of 1507/4953 μA/μm and subthreshold swing of 84/67 mV/dec for the n-/p-type devices, respectively. Our predictions for the n- and p-type WZ-InSb GAA DNW FETs can pave the way to extend Moore’s law for future electronics with the physical size of transistors to the sub-5 nm CMOS-integrated circuits.
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