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<p>Two-dimensional&#xa0;(2D) materials, in particular transition metal dichalcogenides (TMDCs), have been recognized as material class with great potential for future electronic devices. However, to realize the potential of these materials, technology processes are needed that allow wafer-scale fabrication to integrate 2D materials into electronic devices. This paper presents such technology. A wafer-scale sputter deposition process of MoS<sub>2</sub> is presented, which enables a homogeneous coating of SiO<sub>2</sub> wafers. Based on this process, a technology is presented that allows the fabrication of two-terminal devices of different area dimensions at wafer scale. As a critical technological step, the passivation of the MoS<sub>2</sub> layer, in particular, is examined more closely by means of automated electrical measurements at wafer level and chemical–structural investigations using scanning transmission electron microscopy (STEM), among others. We show that the electronic properties of devices with insufficient passivation change significantly. Thus, a protection of the MoS<sub>2</sub> layer during fabrication and for the final operation is of particular importance. By taking this into account, the here designed device technology shows a way to integrate 2D materials into future microelectronic systems.</p>

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Wafer-scale technology for the integration of molybdenum disulfide into vertical electronic device structures

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2025年7月25日

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  • Anna Linkenheil,
  • Theresa Scheler,
  • Bernd Hähnlein,
  • Jonas Schneegaß,
  • Ole Gronenberg,
  • Andrea Knauer,
  • Peter Schaaf,
  • Lorenz Kienle,
  • Martin Ziegler

摘要

Two-dimensional (2D) materials, in particular transition metal dichalcogenides (TMDCs), have been recognized as material class with great potential for future electronic devices. However, to realize the potential of these materials, technology processes are needed that allow wafer-scale fabrication to integrate 2D materials into electronic devices. This paper presents such technology. A wafer-scale sputter deposition process of MoS2 is presented, which enables a homogeneous coating of SiO2 wafers. Based on this process, a technology is presented that allows the fabrication of two-terminal devices of different area dimensions at wafer scale. As a critical technological step, the passivation of the MoS2 layer, in particular, is examined more closely by means of automated electrical measurements at wafer level and chemical–structural investigations using scanning transmission electron microscopy (STEM), among others. We show that the electronic properties of devices with insufficient passivation change significantly. Thus, a protection of the MoS2 layer during fabrication and for the final operation is of particular importance. By taking this into account, the here designed device technology shows a way to integrate 2D materials into future microelectronic systems.