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<p>The Internet of Things (IoT) has grown into an important aspect of daily life, spanning various areas from intelligent industrial automation to healthcare wearable. However, addressing security remains a significant challenge. One way to address this issue is by using cryptographic techniques like Advanced Encryption Standard (AES) for encryption and authentication. The security of AES is rooted in its S-box operations. The proposed work introduces a novel method for producing S-box values needed for encryption through the use of a Non-Linear Feedback Shift Register (NLFSR). By varying the primitive polynomials and seed values of the NLFSR, multiple S-box designs were generated. These S-boxes were examined using standard performance measures of cryptographic properties. The best-performing S-boxes attain a nonlinearity of 98, a strict avalanche value of 0.5615, a bit-independence nonlinearity of 112, a bit-independence strict avalanche value of 0.5614, a linear approximation probability of 0.125, and a differential approximation probability of 0.0391. Notably, the strict avalanche behavior of the proposed S-box exceeds that of the AES S-box and improves upon results reported in earlier studies. Further, the enhanced AES architecture is demonstrated on Basys 3 and Genesys 2 FPGA board.</p>

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A Robust AES Implementation using FPGA with Enhanced Security Features

  • 期刊论文

  • 发表日期：

    2026年1月29日

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  • Arulmurugan Azhaganantham,
  • Vivek Balasubramaniam

摘要

The Internet of Things (IoT) has grown into an important aspect of daily life, spanning various areas from intelligent industrial automation to healthcare wearable. However, addressing security remains a significant challenge. One way to address this issue is by using cryptographic techniques like Advanced Encryption Standard (AES) for encryption and authentication. The security of AES is rooted in its S-box operations. The proposed work introduces a novel method for producing S-box values needed for encryption through the use of a Non-Linear Feedback Shift Register (NLFSR). By varying the primitive polynomials and seed values of the NLFSR, multiple S-box designs were generated. These S-boxes were examined using standard performance measures of cryptographic properties. The best-performing S-boxes attain a nonlinearity of 98, a strict avalanche value of 0.5615, a bit-independence nonlinearity of 112, a bit-independence strict avalanche value of 0.5614, a linear approximation probability of 0.125, and a differential approximation probability of 0.0391. Notably, the strict avalanche behavior of the proposed S-box exceeds that of the AES S-box and improves upon results reported in earlier studies. Further, the enhanced AES architecture is demonstrated on Basys 3 and Genesys 2 FPGA board.