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<p>As semiconductor technologies relentlessly scale, FinFETs have become pivotal for high-performance, power-efficient applications. This study introduces and characterizes a novel defect mechanism specific to FinFET devices, originating from single particle contamination during Self-Aligned Double Patterning (SADP) and Replacement Metal Gate (RMG) fabrication. This defect results in the simultaneous disconnection of two transistor gates from their respective input signals, accompanied by the formation of zero-resistance bridge defects between the two disconnected inputs, as well as between the disconnected gates. Rigorous SPICE simulations reveal that the defect’s electrical signature deviates significantly from conventional fault models, potentially escaping detection by standard test methodologies. We provide guidelines for optimal test vector selection, employing both logic-level functional and delay-based testing, to maximize fault coverage. Furthermore, we analyze the impact of Negative Bias Temperature Instability (NBTI) on the defect’s electrical behavior, demonstrating its influence on circuit reliability. These findings highlight the critical need for specialized test strategies tailored to this unique defect, ultimately enabling the fabrication of FinFET circuits with enhanced quality and reliability.</p>

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A Novel Defect Model Induced by a Single Dust Particle Contamination in the FinFET Gate Fingers

  • 期刊论文

  • 发表日期：

    2025年9月8日

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  • Gustavo Aguirre,
  • Victor Champac,
  • Freddy Forero,
  • Michel Renovell,
  • Leonardo Miceli

摘要

As semiconductor technologies relentlessly scale, FinFETs have become pivotal for high-performance, power-efficient applications. This study introduces and characterizes a novel defect mechanism specific to FinFET devices, originating from single particle contamination during Self-Aligned Double Patterning (SADP) and Replacement Metal Gate (RMG) fabrication. This defect results in the simultaneous disconnection of two transistor gates from their respective input signals, accompanied by the formation of zero-resistance bridge defects between the two disconnected inputs, as well as between the disconnected gates. Rigorous SPICE simulations reveal that the defect’s electrical signature deviates significantly from conventional fault models, potentially escaping detection by standard test methodologies. We provide guidelines for optimal test vector selection, employing both logic-level functional and delay-based testing, to maximize fault coverage. Furthermore, we analyze the impact of Negative Bias Temperature Instability (NBTI) on the defect’s electrical behavior, demonstrating its influence on circuit reliability. These findings highlight the critical need for specialized test strategies tailored to this unique defect, ultimately enabling the fabrication of FinFET circuits with enhanced quality and reliability.