Modelling, Simulation, and FPGA Implementation of an Augmented Memory Built-in Self-Test Based Design for Bit-Oriented Memory
摘要
This paper presents an improved hybrid memory testing approach Galloping with MARCH C- (GALMARC) based Field Programmable Gate Array (FPGA) implementation of Memory Built-in Self-Test (MBIST) design targeted for Bit-Oriented Memory. The conventional memory test Galloping Pattern (GALPAT) can be easily modified using many other galloping patterns that give adequate fault coverage for targeted, dynamic faults. However, its scope is limited to specific dynamic faults only. The March C- memory test provides a better framework to test the variety of static fault classes. Still, the obtained fault coverage is not sufficient. Therefore, the proposed memory testing technique intelligently clubbed the two conventional memory testing algorithms, i.e., GALPAT and March C- algorithms, to improve the fault coverage for both static and dynamic faults. The presented algorithm adheres to the features of its parent algorithms, i.e., GALPAT and MARCH C-. The presented MBIST generates a fault dictionary based on the proposed GALMARC, having fault coverage of transition- faults, stack-at-faults, stuck-open-faults, and some coupling-faults. The proposed MBIST design is also implemented and tested with a memory built-in self-test structure on Virtex-5, xc5vlx30 FPGA. The proposed algorithm GALMARC supports the column first or row first bit-oriented Static Random Access Memory (SRAM) memory. The Memory under Test (MUT) sizes taken for testing are 256 × 8 × 1, 512 × 8 × 1, and 1024 × 8 × 1. Despite having some area overhead and complexity issues, the results justify that the proposed MBIST design based on GALMARC performs better in fault coverage.