<p>ElectroMagnetic Fault Injection (EMFI) attacks have garnered noteworthy attention in the world of embedded secure devices due to the optimal balance between the attack effectiveness and the setup requirements. Since Ring Oscillators (ROs) can be critical components for secure primitives such as True Random Number Generators (TRNGs), Physical Unclonable Functions (PUFs) and on-chip voltage or temperature sensors, their response to this potent threat needs to be fully investigated. In this paper, we contribute to a deeper understanding of EMFI faults by performing single EM pulsed fault injections on ROs implemented in Field-Programmable Gate Arrays (FPGAs). The fault models proposed in the state of the art, such as the Sampling Fault Model and the Timing Fault Model, mainly refer to synchronous logic and are not tuned for asynchronous combinational logic in a loop. Our findings reveal that harmonic locking explains the occurrence of harmonic errors with variable characteristics depending on the different EM pulse settings, the RO placement within the FPGA chip and the manufacturing properties of the FPGA. These findings improve our understanding of EMFI’s impact on different architectures and can be leveraged to design more robust hardware implementations against this attack.</p>

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On the Harmonic Locking of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection in FPGAs

  • Sami El Amraoui,
  • Aghiles Douadi,
  • Régis Leveugle,
  • Paolo Maistri

摘要

ElectroMagnetic Fault Injection (EMFI) attacks have garnered noteworthy attention in the world of embedded secure devices due to the optimal balance between the attack effectiveness and the setup requirements. Since Ring Oscillators (ROs) can be critical components for secure primitives such as True Random Number Generators (TRNGs), Physical Unclonable Functions (PUFs) and on-chip voltage or temperature sensors, their response to this potent threat needs to be fully investigated. In this paper, we contribute to a deeper understanding of EMFI faults by performing single EM pulsed fault injections on ROs implemented in Field-Programmable Gate Arrays (FPGAs). The fault models proposed in the state of the art, such as the Sampling Fault Model and the Timing Fault Model, mainly refer to synchronous logic and are not tuned for asynchronous combinational logic in a loop. Our findings reveal that harmonic locking explains the occurrence of harmonic errors with variable characteristics depending on the different EM pulse settings, the RO placement within the FPGA chip and the manufacturing properties of the FPGA. These findings improve our understanding of EMFI’s impact on different architectures and can be leveraged to design more robust hardware implementations against this attack.