It has been known and explored for many years that low voltage testing amplifies the effect of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning SDFs into easily detectable stuck-at-faults. It is often overlooked that \(V_{\textrm{min}}\) testing poses an additional challenge to the test pattern generation method under process variations. The standard deviation of gate delays under \(V_{\textrm{min}}\) is a multiple of that under nominal voltage. The increased variation will invalidate the efficiency of test patterns generated under nominal voltage and significantly reduce fault coverage. This paper presents the first algorithm for test pattern generation specifically tuned for \(V_{\textrm{min}}\) testing which obtains higher fault coverage by smaller test sets than those generated for nominal voltage. The patterns applicable to other voltage levels can be derived from the pattern set generated under extreme variations at low supply voltage. Experimental results demonstrate that the proposed method produces test patterns that outperform N-detection test sets in terms of test set volume and fault efficiency across different voltage levels.
