<p>SRAM-based FPGAs are highly valued for their superior configurability, high performance, and fast operational speeds, leading to widespread application across various fields. However, the numerous memory cells in these devices are susceptible to single-event upset (SEU), especially in radiation environments, posing significant challenges to system reliability and robustness. This paper proposes a circuit modification model and corresponding fault injection strategy to simulate SEU phenomena in the user memory of SRAM-based FPGAs. We built a fault injection platform based on the proposed model and strategy, and experimental validation confirmed its effectiveness. The experimental results show that the platform can effectively simulate SEUs occurring at random operational moments and accurately assess the impact of SEUs on the circuit.</p>

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SEU Fault Injection Strategy for SRAM-based FPGA User Memory Based on Dual-Circuit Model

  • Yuchao Liu,
  • Liang Yao,
  • Wenjing Zhang,
  • Yuhao Wang,
  • XinKai Jiang,
  • FuSen Li,
  • Qiu Xu

摘要

SRAM-based FPGAs are highly valued for their superior configurability, high performance, and fast operational speeds, leading to widespread application across various fields. However, the numerous memory cells in these devices are susceptible to single-event upset (SEU), especially in radiation environments, posing significant challenges to system reliability and robustness. This paper proposes a circuit modification model and corresponding fault injection strategy to simulate SEU phenomena in the user memory of SRAM-based FPGAs. We built a fault injection platform based on the proposed model and strategy, and experimental validation confirmed its effectiveness. The experimental results show that the platform can effectively simulate SEUs occurring at random operational moments and accurately assess the impact of SEUs on the circuit.