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<p>Fault-tolerance and dependable digital systems are now used in a diverse set of safety critical and cyber physical systems (CPSs) applications like healthcare instrumentation and control (I&amp;C) devices, aerospace, smart cities, and military systems. The architectural design principles required for achieving dependability in these systems vary as much as the safety-critical CPS system formal requirements and specifications. CPSs are composed of embedded hardware, specialized software, algorithms, and computation-based models interconnected to integrate computational and physical components. In this paper, we present the design, modeling and simulation of a reliable and secure microcontroller-based hardware architecture using a heterogenous design approach that combines concepts from computer-based architectural system design, state machine diagram, and traditional fault-tolerance, and defense in depth techniques. The proposed dependable architecture consists of a variety of software and hardware components: a sensing unit, a processing unit, and an actuating unit, interconnected to monitor the status of different physical quantities such as temperature, water and gas physical quantities. The simulation-based experimental results demonstrate the resilient operation of the proposed fault-tolerant hardware CPS system that achieves the highest reliability 0.999833345 with the failure-rate 0.03 failure per hour at the time equal to 15&#xa0;min and how it is used in executing safety and security tasks. The reliability level of the TMR system remains high in the three different failure rate assumptions and is not less than 0.98. Consequently, we think that using such fault tolerant hardware architectures with the failure rate 0.03 failure per hour in embedded systems will lead to strengthen the reliability of next generation smart-home CPS applications.&#xa0;</p>

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Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems

  • 期刊论文

  • 发表日期：

    2025年2月13日

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  • Hamed A. Mahmood,
  • Shawkat S. Khairullah

摘要

Fault-tolerance and dependable digital systems are now used in a diverse set of safety critical and cyber physical systems (CPSs) applications like healthcare instrumentation and control (I&C) devices, aerospace, smart cities, and military systems. The architectural design principles required for achieving dependability in these systems vary as much as the safety-critical CPS system formal requirements and specifications. CPSs are composed of embedded hardware, specialized software, algorithms, and computation-based models interconnected to integrate computational and physical components. In this paper, we present the design, modeling and simulation of a reliable and secure microcontroller-based hardware architecture using a heterogenous design approach that combines concepts from computer-based architectural system design, state machine diagram, and traditional fault-tolerance, and defense in depth techniques. The proposed dependable architecture consists of a variety of software and hardware components: a sensing unit, a processing unit, and an actuating unit, interconnected to monitor the status of different physical quantities such as temperature, water and gas physical quantities. The simulation-based experimental results demonstrate the resilient operation of the proposed fault-tolerant hardware CPS system that achieves the highest reliability 0.999833345 with the failure-rate 0.03 failure per hour at the time equal to 15 min and how it is used in executing safety and security tasks. The reliability level of the TMR system remains high in the three different failure rate assumptions and is not less than 0.98. Consequently, we think that using such fault tolerant hardware architectures with the failure rate 0.03 failure per hour in embedded systems will lead to strengthen the reliability of next generation smart-home CPS applications.