Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization

A novel approach to achieve low power consumption during Built-In Self-Test (BIST) operations in Very Large Scale Integrated (VLSI) circuits through the integration of Generative Adversarial Networks (GANs) in the test pattern generation process is presented in this work. The escalating need for energy-efficient VLSI designs necessitates novel approaches to reduce power consumption without compromising fault coverage. This research capitalizes on GANs to create an adaptive and optimized test pattern generator for low-power BIST architectures. GANs comprise a generator and discriminator, with the generator learning to create authentic data and the discriminator distinguishing real from generated data. By employing GANs, the BIST framework captures intricate patterns, enabling custom test patterns for specific circuit attributes. Data collection from circuits under test is followed by pre-processing for GAN training. The trained GAN generates diverse test patterns, optimized for both low power consumption and heightened fault coverage. This GAN-based test pattern generator seamlessly integrates into the BIST architecture, including Ternary Parallel Prefix Tree Adder (TPPTA). Comprehensive evaluations validate the superiority of the GAN-enhanced BIST, showcasing significant power reduction, elevated fault detection, and reduced testing duration.