A SLvT Adaptive Test Method for Integrated Circuit Test Parameter Sets without Yield Loss

With the development of semiconductor technology, the fabrication process of integrated circuits is complicated and expensive, and the testing of integrated circuits has become increasingly difficult. The reduction of testing costs has become a very important issue, and how to reduce the yield loss caused by testing has become increasingly important. Therefore, an adapted SLvT(Simplified Loss recovery Test) methodology is proposed, leveraging historical wafer data. Initially, the approach employs RFECV (Recursive Feature Elimination with Cross-Validation) and Pearson correlation analysis to sequentially select pivotal parameters., and XGBoost is used to achieve accurate prediction. For chips predicted as faulty, additional parameter items are added using the MI (Mutual Information) method improved by normal distribution. Prediction is then achieved through the retrained XGBoost., which greatly reduces the test yield loss. Finally, the chips that are predicted to be bad are fully tested to achieve zero yield loss. In addition, experimental validation underscores the efficacy of the method, demonstrating a substantial decrease in test resource occupancy, only 32.5%, at the expense of only 0.09% of test escape. At the same time, compared with other adaptive methods, the performance of zero yield loss is better than 83.5%