Fatigue Life Based Study of Electronic Package Mounting Locations on Printed Circuit Boards Subjected to Random Vibration Loads

Plastic Ball Grid Array (PBGA) packages (chips) mounted on a Printed Circuit Board (PCB) assembly are vulnerable and are more likely to fail when they are subjected to random vibration environmental conditions. The proper positioning of the packages on the PCB also influences the magnitude of the dynamic stresses induced in the vulnerable solder joints of the PCB assembly. In this work, an effort is made to identify the best location for positioning the packages on the PCB, which are subjected to severe random vibration load conditions. Investigations have been carried out by designing and fabricating a multi-chip PCB assembly and several single-chip PCB assemblies (chips mounted at different locations on the PCB) as per JEDEC standards. By subjecting these packages to random white noise input, numerical analysis and experiments were sought to identify the vulnerability of the packages to various mounting locations in a novel way. Based on the response stress PSD on the solder joints, the fatigue life of the PCB assembly was calculated. The results showed that the fatigue life of the PCB assembly with PBGA package at the U6A position is significantly higher when compared with that of a package at the center position of the PCB.