Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements

Establishing a general and high-quality testing method for fabricated asynchronous circuits is crucial for the widespread adoption of asynchronous circuits. A full scan design for asynchronous circuits is imperative to address the major issue of manufacturing reliability. To establish a comprehensive testing workflow for asynchronous circuits, verification and validation are required for evaluating the full scan design must be conducted from gate level to chip level. Therefore, this paper proposes layout level circuits corresponding to transistor level scan elements capable of achieving a full scan design for general asynchronous circuits utilizing the Rohm \(0.18\mathrm {\, [\mu m]}\) $0.18[\mu \mathrm{m}]$ process technology. Moreover, a prototype chip fabricated from the taped-out layout level circuits is utilized for verification and validation on both the layout and chip levels. As the verification and validation results at the layout level, the area and delay overhead against the original C-element and the scan C-elements were evaluated. Furthermore, the prototype real chip implementing the proposed scan C-elements was mounted onto a chip tester for dynamic verification by simulation, and the functional delay was measured by observing the signals with an oscilloscope. The usefulness of the proposed scan C-elements in the real chip has shown that it can be utilized as a library to realize a full scan design of asynchronous circuits.