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<p>In this study, we optimize the reprogram scheme in program operation of a&#xa0;3D NAND flash memory based on device-level simulations. To enhance the reliability during program operation, it is crucial to reduce the width of the threshold voltage (V<sub>th</sub>) distribution. For this purpose, commonly used schemes in industrial practice, such as incremental step pulse programming (ISPP) and reprogram, are incorporated. The simulations utilize a physical device model and statistically consider key variability sources, including electron injection spread (EIS), random telegraph noise (RTN), and Z-interference. Furthermore, the impact of short-term retention caused by rapid electron loss in the charge trap layer (CTL) is included in program simulation and analyzed. Results of simulation are calibrated using machine learning-based data fitting. Finally, using this simulation framework, the optimization identifies conditions that minimize the V<sub>th</sub> distribution width without degrading other device characteristics, using interpolation in distribution width contour. The proposed approach is quantitatively compared with conventional methods, demonstrating significant improvement.</p>

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Developing an ultimate 3D NAND flash memory simulation environment for operation and optimization

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年7月30日

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  • Jooyoung Lee,
  • Jinil Yoo,
  • Hyungcheol Shin

摘要

In this study, we optimize the reprogram scheme in program operation of a 3D NAND flash memory based on device-level simulations. To enhance the reliability during program operation, it is crucial to reduce the width of the threshold voltage (Vth) distribution. For this purpose, commonly used schemes in industrial practice, such as incremental step pulse programming (ISPP) and reprogram, are incorporated. The simulations utilize a physical device model and statistically consider key variability sources, including electron injection spread (EIS), random telegraph noise (RTN), and Z-interference. Furthermore, the impact of short-term retention caused by rapid electron loss in the charge trap layer (CTL) is included in program simulation and analyzed. Results of simulation are calibrated using machine learning-based data fitting. Finally, using this simulation framework, the optimization identifies conditions that minimize the Vth distribution width without degrading other device characteristics, using interpolation in distribution width contour. The proposed approach is quantitatively compared with conventional methods, demonstrating significant improvement.