Scholarlink

<p>With the rapid advancement of chip integration adhering to Moore’s Law, local hotspots within the chip have emerged as critical factors influencing chip functionality and reliability. Traditional research into circuit-level chip thermal distribution remains focused on 2D planar structure analysis. To address the absence of 3D structure thermal analysis at circuit level, a novel methodology for 3D chip thermal analysis at semiconductor transistor level is proposed. By utilizing the chip layout file (GDSII file), the 3D structure is constructed and exported in STP format, compatible with COMSOL, which is a COMSOL. This enables the analysis of transistor-level 3D thermal distribution. The effectiveness of this method is validated through a practical case study involving circuit-level chip thermal analysis.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

3D thermal analysis at transistor level based on IC layout files

  • 期刊论文

  • 发表日期：

    2026年4月25日

查看全文
  • Kaili Ding,
  • Kai Sun,
  • Maozheng Liu,
  • Haihang Cui

摘要

With the rapid advancement of chip integration adhering to Moore’s Law, local hotspots within the chip have emerged as critical factors influencing chip functionality and reliability. Traditional research into circuit-level chip thermal distribution remains focused on 2D planar structure analysis. To address the absence of 3D structure thermal analysis at circuit level, a novel methodology for 3D chip thermal analysis at semiconductor transistor level is proposed. By utilizing the chip layout file (GDSII file), the 3D structure is constructed and exported in STP format, compatible with COMSOL, which is a COMSOL. This enables the analysis of transistor-level 3D thermal distribution. The effectiveness of this method is validated through a practical case study involving circuit-level chip thermal analysis.