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<p>As heterogeneous integration advances toward higher power density, thermal management has become a critical issue for 2.5D system performance and reliability. Existing approaches often treat chiplet placement and through-silicon via (TSV) insertion as independent optimization tasks, which may limit the achievable thermal performance. This paper proposes a two-stage strategy that jointly optimizes chiplet placement and TSV distribution. In Stage I, an improved particle swarm optimization (PSO) algorithm with elite learning and adaptive mutation is proposed to minimize peak temperature, total wirelength, and layout area under physical constraints. In Stage II, a Gaussian process regression (GPR)-based surrogate model is constructed to replace computationally expensive finite element thermal simulations, enabling rapid thermal prediction of TSV spatial configurations. This surrogate model drives a genetic algorithm to optimize TSV configurations in local hotspot regions. Additionally, this work investigates the impact of emerging high thermal conductivity materials, such as single-walled and multi-walled carbon nanotubes, on TSV thermal performance and provides a systematic comparison with traditional copper TSVs. Experimental results demonstrate that the proposed strategy achieves a maximum reduction of 10&#xa0;K in peak temperature after TSV insertion, significantly enhances temperature uniformity, and reduces the optimization evaluation time to 2.7s. Importantly, the results reveal that TSV spatial distribution plays a more dominant role in thermal management than intrinsic material thermal conductivity, offering new insights for next-generation high-performance packaging technologies.</p>

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A two-stage thermal-aware design strategy for chiplet placement and TSV optimization in 2.5D integrated systems

  • 期刊论文

  • 发表日期：

    2026年5月19日

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  • Zhangxi Xia,
  • Zhongliang Pan

摘要

As heterogeneous integration advances toward higher power density, thermal management has become a critical issue for 2.5D system performance and reliability. Existing approaches often treat chiplet placement and through-silicon via (TSV) insertion as independent optimization tasks, which may limit the achievable thermal performance. This paper proposes a two-stage strategy that jointly optimizes chiplet placement and TSV distribution. In Stage I, an improved particle swarm optimization (PSO) algorithm with elite learning and adaptive mutation is proposed to minimize peak temperature, total wirelength, and layout area under physical constraints. In Stage II, a Gaussian process regression (GPR)-based surrogate model is constructed to replace computationally expensive finite element thermal simulations, enabling rapid thermal prediction of TSV spatial configurations. This surrogate model drives a genetic algorithm to optimize TSV configurations in local hotspot regions. Additionally, this work investigates the impact of emerging high thermal conductivity materials, such as single-walled and multi-walled carbon nanotubes, on TSV thermal performance and provides a systematic comparison with traditional copper TSVs. Experimental results demonstrate that the proposed strategy achieves a maximum reduction of 10 K in peak temperature after TSV insertion, significantly enhances temperature uniformity, and reduces the optimization evaluation time to 2.7s. Importantly, the results reveal that TSV spatial distribution plays a more dominant role in thermal management than intrinsic material thermal conductivity, offering new insights for next-generation high-performance packaging technologies.