Scholarlink

<p>This study introduces a new memtranstor emulator circuit using second-generation current conveyors (CCII), providing an alternative to the only existing memtranstor emulator circuit in the literature. The proposed circuit consists of three CCIIs, one analog multiplier (AD633), two grounded resistors, and three grounded capacitors. The design is implemented using 180&#xa0;nm CMOS technology, and its functionality is validated through PSPICE simulations. The circuit’s behavior is analyzed under various conditions including pinched hysteresis loops, Monte Carlo analysis, memory effect simulations, and temperature variation tests, all of which confirm its proper operation. Additionally, the circuit can be easily adapted between incremental and decremental memory emulators, demonstrating its versatility for various applications. The proposed emulator has been further validated through experimental implementation, confirming its feasibility for practical applications. A memtranstor-based chaotic oscillator is presented as an application example. Compared to the existing design in the literature, the proposed emulator offers several key advantages: It employs fewer active and passive components, leading to a simpler structure with the potential for more compact implementation. The absence of operational amplifiers (op-amps) improves bandwidth performance by eliminating the fixed gain-bandwidth product limitation, enabling higher gain levels at broader bandwidths. Additionally, the use of low-power CMOS parameters potentially allows for lower supply voltages, which, along with fewer components, can significantly reduce power consumption.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Design of a novel memtranstor emulator using CCIIs and experimental validation

  • 期刊论文

  • 发表日期：

    2025年9月25日

查看全文
  • Muzaffer Çayır,
  • Mehmet Sağbaş

摘要

This study introduces a new memtranstor emulator circuit using second-generation current conveyors (CCII), providing an alternative to the only existing memtranstor emulator circuit in the literature. The proposed circuit consists of three CCIIs, one analog multiplier (AD633), two grounded resistors, and three grounded capacitors. The design is implemented using 180 nm CMOS technology, and its functionality is validated through PSPICE simulations. The circuit’s behavior is analyzed under various conditions including pinched hysteresis loops, Monte Carlo analysis, memory effect simulations, and temperature variation tests, all of which confirm its proper operation. Additionally, the circuit can be easily adapted between incremental and decremental memory emulators, demonstrating its versatility for various applications. The proposed emulator has been further validated through experimental implementation, confirming its feasibility for practical applications. A memtranstor-based chaotic oscillator is presented as an application example. Compared to the existing design in the literature, the proposed emulator offers several key advantages: It employs fewer active and passive components, leading to a simpler structure with the potential for more compact implementation. The absence of operational amplifiers (op-amps) improves bandwidth performance by eliminating the fixed gain-bandwidth product limitation, enabling higher gain levels at broader bandwidths. Additionally, the use of low-power CMOS parameters potentially allows for lower supply voltages, which, along with fewer components, can significantly reduce power consumption.