Scholarlink

<p>Traditional analytical models derived for Si logic devices fail to estimate the threshold voltage (<i>V</i><sub><i>TH</i></sub>) of vertical junctionless GaN power Fin-channel metal oxide semiconductor field effect transistors (VJ GaN Fin-MOSFETs). Solving two-dimensional Poisson’s equation inside the drift region of VJ GaN Fin- MOSFETs is not a viable option as of now. Thus, we report an alternate methodology to derive the analytical model for estimating the <i>V</i><sub><i>TH</i></sub> of VJ GaN Fin-MOSFETs. The proposed model uses an available baseline model followed by adding tuning parameters to the baseline model via a standard procedure. The proposed model faithfully predicts the effect of crucial geometrical and bias parameters on <i>V</i><sub><i>TH</i></sub>; along with estimating the drain induced barrier lowering effect. The proposed methodology is generic in nature; it can be applied to other (ultra)wide bandgap semiconductor based VJ power MOSFETs that are currently under extensive investigation.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

On estimating the threshold voltage of vertical junctionless GaN power fin-MOSFETs

  • 期刊论文

  • 发表日期：

    2025年9月6日

查看全文
  • Smriti Singh,
  • Ankita Mukherjee,
  • Aasim Ashai,
  • Tanmoy Pramanik,
  • Biplab Sarkar

摘要

Traditional analytical models derived for Si logic devices fail to estimate the threshold voltage (VTH) of vertical junctionless GaN power Fin-channel metal oxide semiconductor field effect transistors (VJ GaN Fin-MOSFETs). Solving two-dimensional Poisson’s equation inside the drift region of VJ GaN Fin- MOSFETs is not a viable option as of now. Thus, we report an alternate methodology to derive the analytical model for estimating the VTH of VJ GaN Fin-MOSFETs. The proposed model uses an available baseline model followed by adding tuning parameters to the baseline model via a standard procedure. The proposed model faithfully predicts the effect of crucial geometrical and bias parameters on VTH; along with estimating the drain induced barrier lowering effect. The proposed methodology is generic in nature; it can be applied to other (ultra)wide bandgap semiconductor based VJ power MOSFETs that are currently under extensive investigation.