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<p>In this work, a novel drain-side lateral heterojunction architecture is proposed to effectively suppress ambipolar conduction in tunnel FETs (TFETs). The proposed lateral heterojunction features a large bandgap GaAsP pocket on the drain side, forming a heterojunction at the channel/drain junction of the TFET. Since large bandgap materials exhibit a lower band-to-band tunneling rate, the GaAsP drain pocket efficiently reduces ambipolarity in both Si and non-Si-TFETs. Furthermore, well-calibrated device simulation results show that the proposed GaAsP drain pocket TFET with optimized pocket length provides superior performance in terms of reduced ambipolarity compared to conventional TFETs and TFETs with&#xa0;other possible structural modifications at the channel/drain interface using GaAsP. It is well known that both ambipolar behavior and capacitance values play a critical role for the successful operation of TFET-based high-speed logic circuits. Therefore, the impact of the GaAsP drain pocket on capacitance and intrinsic time delay is also critically evaluated.</p>

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Suppression of ambipolarity without compromising delay using drain-side lateral heterojunction for future TFETs

  • 期刊论文

  • 发表日期：

    2025年8月18日

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  • Sayani Ghosh,
  • Priyajit Mukherjee,
  • Hafizur Rahaman

摘要

In this work, a novel drain-side lateral heterojunction architecture is proposed to effectively suppress ambipolar conduction in tunnel FETs (TFETs). The proposed lateral heterojunction features a large bandgap GaAsP pocket on the drain side, forming a heterojunction at the channel/drain junction of the TFET. Since large bandgap materials exhibit a lower band-to-band tunneling rate, the GaAsP drain pocket efficiently reduces ambipolarity in both Si and non-Si-TFETs. Furthermore, well-calibrated device simulation results show that the proposed GaAsP drain pocket TFET with optimized pocket length provides superior performance in terms of reduced ambipolarity compared to conventional TFETs and TFETs with other possible structural modifications at the channel/drain interface using GaAsP. It is well known that both ambipolar behavior and capacitance values play a critical role for the successful operation of TFET-based high-speed logic circuits. Therefore, the impact of the GaAsP drain pocket on capacitance and intrinsic time delay is also critically evaluated.