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<p>Characteristics inherent to nonplanar geometries, with an aim to reduce program/erase voltages in ferroelectric field-effect transistor (FE-FET)-based memory devices, are proposed. The basis is the enhancement of the electric field in the FE films integrated with Fin-based FE-FETs (FE-FinFET), compared to FE films in planar FE-FETs. A new design (DE/FE-FinFET), based on combining FE and dielectric (DE) materials in the gate stack of FinFETs, is also proposed. Modeling and technology computer-aided design simulations indicate larger memory window at lower voltages in Fin-based FE-FETs. It is found that with nonplanar geometries a memory window can be observed at voltages 11% lower with FE-FinFETs and 33% lower with DE/FE-FinFETs compared to planar configurations.</p>

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Low-voltage polarization switching in ferroelectric FinFET-based memory devices, using electric field nonlinearities

  • 期刊论文

  • 发表日期：

    2025年5月31日

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  • Shreyam Natani,
  • P. R. Bandaru

摘要

Characteristics inherent to nonplanar geometries, with an aim to reduce program/erase voltages in ferroelectric field-effect transistor (FE-FET)-based memory devices, are proposed. The basis is the enhancement of the electric field in the FE films integrated with Fin-based FE-FETs (FE-FinFET), compared to FE films in planar FE-FETs. A new design (DE/FE-FinFET), based on combining FE and dielectric (DE) materials in the gate stack of FinFETs, is also proposed. Modeling and technology computer-aided design simulations indicate larger memory window at lower voltages in Fin-based FE-FETs. It is found that with nonplanar geometries a memory window can be observed at voltages 11% lower with FE-FinFETs and 33% lower with DE/FE-FinFETs compared to planar configurations.