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<p>This paper presents the design and evaluation of a light-weight RISC-V-based microcontroller targeted for embedded and real-time applications. Leveraging the modularity and openness of the RISC-V instruction set architecture (ISA), the proposed single-cycle MCU integrates the RV32I base ISA with custom bit manipulation instructions that reduce instruction count and improve execution efficiency, peripheral subsystems, and a datapath-optimized design to deliver energy-efficient performance. Major peripherals, including UART, GPIO, timers, and interrupt controllers, are seamlessly included in a memory-mapped manner to simplify system development. The MCU was synthesized in Verilog HDL and implemented on the Xilinx Artix-7 FPGA platform. Moreover, functional correctness is verified using standard RISC-V compliance tests. Experimental results demonstrate favorable trade-offs among performance, resource consumption, and power efficiency when compared with available RISC-V soft cores and commercial microcontrollers.</p>

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Design and implementation of a single-cycle RISC-V microcontroller with custom ISA extensions and peripheral integration

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年7月17日

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  • Rachit Srivastava,
  • Utkarsh Kumar,
  • Mohita Jaiswal,
  • Abhishek Sharma,
  • Sulabh Bansal

摘要

This paper presents the design and evaluation of a light-weight RISC-V-based microcontroller targeted for embedded and real-time applications. Leveraging the modularity and openness of the RISC-V instruction set architecture (ISA), the proposed single-cycle MCU integrates the RV32I base ISA with custom bit manipulation instructions that reduce instruction count and improve execution efficiency, peripheral subsystems, and a datapath-optimized design to deliver energy-efficient performance. Major peripherals, including UART, GPIO, timers, and interrupt controllers, are seamlessly included in a memory-mapped manner to simplify system development. The MCU was synthesized in Verilog HDL and implemented on the Xilinx Artix-7 FPGA platform. Moreover, functional correctness is verified using standard RISC-V compliance tests. Experimental results demonstrate favorable trade-offs among performance, resource consumption, and power efficiency when compared with available RISC-V soft cores and commercial microcontrollers.