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<p>Cryptography plays a crucial role in ensuring security in modern computer systems. The Advanced Encryption Standard (AES) has become more important for protecting data and enabling end-to-end encrypted communication. This work offers an innovative architectural optimization method using Verilog Hardware Description Language (HDL). This research introduces a novel approach to data encryption employing a chaotic-based AES S-box. A further layer of protection is added by using chaotic maps, which are sensitive and random by nature. The substitution values inside the chaotic-based S-box are continuously changed during the encryption procedure. The proposed design maintains strong encryption characteristics while achieving efficient hardware performance. Moreover, the design incorporates parallelization techniques to reduce the delay associated with encryption and decryption operations for AddRoundKey and MixColumns transformations. The proposed design is implemented on a Xilinx Virtex-7 Field Programmable Gate Array (FPGA) and is assessed using the Xilinx ISE 14.7 suite. The proposed AES architecture achieves an encryption latency of 24.543&#xa0;ns and a decryption latency of 35.638&#xa0;ns, operating at a maximum frequency of 245.853&#xa0;MHz. The design utilizes 9,450 LUTs for encryption and 11,995 LUTs for decryption, with power consumption of 275&#xa0;mW and 310&#xa0;mW, respectively. A throughput of 1.28&#xa0;Gbps for encryption and 0.88&#xa0;Gbps for decryption is achieved, demonstrating suitability for real-time secure communication. The evaluation results show a significant reduction in delay and hardware resource usage for both encryption and decryption. The proposed approach provides a fast and efficient solution for secure data transmission, demonstrating competitive performance compared to existing AES-based implementations. The approach presented in this study offers a feasible method to balance robust security and effective data processing in communication systems.</p>

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Enhanced advanced encryption standard algorithm for secure communication with low latency using verilog hardwaredescription language

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年3月7日

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  • Raju Veerati,
  • Kumar Dorthi,
  • Kiran Siripuri,
  • Srinivas Kuntamalla,
  • Ravi Kanth Kotha

摘要

Cryptography plays a crucial role in ensuring security in modern computer systems. The Advanced Encryption Standard (AES) has become more important for protecting data and enabling end-to-end encrypted communication. This work offers an innovative architectural optimization method using Verilog Hardware Description Language (HDL). This research introduces a novel approach to data encryption employing a chaotic-based AES S-box. A further layer of protection is added by using chaotic maps, which are sensitive and random by nature. The substitution values inside the chaotic-based S-box are continuously changed during the encryption procedure. The proposed design maintains strong encryption characteristics while achieving efficient hardware performance. Moreover, the design incorporates parallelization techniques to reduce the delay associated with encryption and decryption operations for AddRoundKey and MixColumns transformations. The proposed design is implemented on a Xilinx Virtex-7 Field Programmable Gate Array (FPGA) and is assessed using the Xilinx ISE 14.7 suite. The proposed AES architecture achieves an encryption latency of 24.543 ns and a decryption latency of 35.638 ns, operating at a maximum frequency of 245.853 MHz. The design utilizes 9,450 LUTs for encryption and 11,995 LUTs for decryption, with power consumption of 275 mW and 310 mW, respectively. A throughput of 1.28 Gbps for encryption and 0.88 Gbps for decryption is achieved, demonstrating suitability for real-time secure communication. The evaluation results show a significant reduction in delay and hardware resource usage for both encryption and decryption. The proposed approach provides a fast and efficient solution for secure data transmission, demonstrating competitive performance compared to existing AES-based implementations. The approach presented in this study offers a feasible method to balance robust security and effective data processing in communication systems.