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<p>Detailed timing models are indispensable tools for the design space exploration of Multiprocessor Systems on Chip (MPSoCs). As core counts continue to increase, the complexity in memory hierarchies and interconnect topologies is also growing, making accurate predictions of design decisions more challenging than ever. In this context, the open-source Full System Simularor (FSS) gem5 is a popular choice for MPSoC design space exploration, thanks to its flexibility and robust set of detailed timing models. However, its single-threaded simulation kernel severely hampers its throughput. To address this challenge, we introduce <i>parti-gem5</i>, an extension of gem5 that enables parallel timing simulations on modern multi-core simulation hosts. Unlike previous works, <i>parti-gem5</i> supports gem5’s timing mode, the <Emphasis FontCategory="NonProportional">O3CPU</Emphasis>, and Ruby’s custom cache and interconnect models. Compared to reference single-thread simulations, we achieved speedups of up to 42.7<InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\times\)</EquationSource> </InlineEquation> when simulating a 120-core ARM MPSoC on a 64-core x86-64 host system. While our method introduces timing deviations, we show that these can be minimised by setting a quantum based on the latencies of the target system. A quantum value just below the hit latency of the shared cache leads to an error in simulated time below 5%. Using this setting, <i>parti-gem5</i> can deliver reliable key activity indicators such as power states and operation counters for CPU, cache and DRAM modules. The combined Mean Absolute Percentage Error (MAPE) for these metrics is 2.62%.</p>

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Scalable and Accurate Parallel Timing Simulations with parti-gem5

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年6月29日

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  • José Cubero-Cascante,
  • Niko Zurstraßen,
  • Jörn Nöller,
  • Rainer Leupers,
  • Jan Moritz Joseph

摘要

Detailed timing models are indispensable tools for the design space exploration of Multiprocessor Systems on Chip (MPSoCs). As core counts continue to increase, the complexity in memory hierarchies and interconnect topologies is also growing, making accurate predictions of design decisions more challenging than ever. In this context, the open-source Full System Simularor (FSS) gem5 is a popular choice for MPSoC design space exploration, thanks to its flexibility and robust set of detailed timing models. However, its single-threaded simulation kernel severely hampers its throughput. To address this challenge, we introduce parti-gem5, an extension of gem5 that enables parallel timing simulations on modern multi-core simulation hosts. Unlike previous works, parti-gem5 supports gem5’s timing mode, the O3CPU, and Ruby’s custom cache and interconnect models. Compared to reference single-thread simulations, we achieved speedups of up to 42.7 \(\times\) when simulating a 120-core ARM MPSoC on a 64-core x86-64 host system. While our method introduces timing deviations, we show that these can be minimised by setting a quantum based on the latencies of the target system. A quantum value just below the hit latency of the shared cache leads to an error in simulated time below 5%. Using this setting, parti-gem5 can deliver reliable key activity indicators such as power states and operation counters for CPU, cache and DRAM modules. The combined Mean Absolute Percentage Error (MAPE) for these metrics is 2.62%.