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<p>FPGAs are promising accelerators for scientific computing tasks because of their potential for delivering high performance-per-Watt. However, programming for optimal performance remains a complex task. Our goal is to bring FPGAs within the reach of domain scientists by developing compilers targeting scientific Fortran code. In this paper, we present a novel approach to aggressively reduce memory utilisation of stencil-based finite-difference Fortran code through a compiler-based automatic program transformation that trades memory accesses for computation. The key contribution of this work is a set of type-driven rewrite rules that identify and eliminate the intermediate arrays in stencil computations and replace them with re-computation, thus reducing the number of memory accesses. The main novelty lies in the transformations to move stencil operations out of maps and folds and to fuse stencils. We demonstrate the effectiveness of our approach using a set of five 3-D and 2-D stencil benchmarks evaluated on an Intel Arria 10 FPGA board. Our transformation result on average in a <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(2.5\times\)</EquationSource> </InlineEquation> reduction in DRAM usage, a <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(3.4\times\)</EquationSource> </InlineEquation> increase in DSP usage, and a <InlineEquation ID="IEq3"> <EquationSource Format="TEX">\(25\times\)</EquationSource> </InlineEquation> improvement in throughput. We show on a real-world exemplar, the Large Eddy Simulator for Urban Flows, that our algorithm successfully removes all intermediate arrays (18 in total), reducing the memory footprint by a factor of <InlineEquation ID="IEq4"> <EquationSource Format="TEX">\(4.5\times\)</EquationSource> </InlineEquation>. The memory-reduced FPGA code, automatically transpiled from the original Fortran source, is <InlineEquation ID="IEq5"> <EquationSource Format="TEX">\(9.7\times\)</EquationSource> </InlineEquation> faster than the original Fortran code, and performance competitive with a hand optimised FPGA version while supporting a four times larger domain size.</p>

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Optimising Stencil Code on FPGAs by Trading Data Movement for Compute using Compiler Rewrite Rules

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年3月2日

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  • Robert Szafarczyk,
  • Syed Waqar Nabi,
  • Wim Vanderbauwhede

摘要

FPGAs are promising accelerators for scientific computing tasks because of their potential for delivering high performance-per-Watt. However, programming for optimal performance remains a complex task. Our goal is to bring FPGAs within the reach of domain scientists by developing compilers targeting scientific Fortran code. In this paper, we present a novel approach to aggressively reduce memory utilisation of stencil-based finite-difference Fortran code through a compiler-based automatic program transformation that trades memory accesses for computation. The key contribution of this work is a set of type-driven rewrite rules that identify and eliminate the intermediate arrays in stencil computations and replace them with re-computation, thus reducing the number of memory accesses. The main novelty lies in the transformations to move stencil operations out of maps and folds and to fuse stencils. We demonstrate the effectiveness of our approach using a set of five 3-D and 2-D stencil benchmarks evaluated on an Intel Arria 10 FPGA board. Our transformation result on average in a \(2.5\times\) reduction in DRAM usage, a \(3.4\times\) increase in DSP usage, and a \(25\times\) improvement in throughput. We show on a real-world exemplar, the Large Eddy Simulator for Urban Flows, that our algorithm successfully removes all intermediate arrays (18 in total), reducing the memory footprint by a factor of \(4.5\times\) . The memory-reduced FPGA code, automatically transpiled from the original Fortran source, is \(9.7\times\) faster than the original Fortran code, and performance competitive with a hand optimised FPGA version while supporting a four times larger domain size.