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<p>This paper presents a 28–42&#xa0;GHz digitally controlled variable-gain amplifier (VGA) with low phase variation for phased-array applications. Comparative analysis of traditional cascode current-canceling topologies reveals that the dominant contributors to phase errors are the drain–source parasitic capacitances (C<sub>ds</sub>) of common-gate transistors. To address this, a novel common-source current-canceling (CSCC) architecture incorporating a cross-connected transistor neutralization (CCTN) technique is proposed, effectively reducing phase error and enhancing isolation and stability. Furthermore, to simultaneously extend bandwidth and increase gain, the amplifier stage adopts a cascode configuration with an RCL feedback loop, combined with broadband transformer matching networks for wideband impedance transformation. The proposed VGA is fabricated in the 65-nm FD-SOI CMOS process, achieving a peak gain of 7&#xa0;dB and a gain-control range (GCR) of 12&#xa0;dB. Across the 3-dB bandwidth from 28 to 42&#xa0;GHz, the phase variation is less than ± 5.6°, and the root-mean-square (RMS) phase error is 1.4°. The VGA core occupies 0.07 mm2 and consumes 21.8 mW from a 1.2&#xa0;V supply.</p>

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A Broadband Low Phase Variation Variable Gain Amplifier with Novel Common Source Current Canceling Technique in 65-nm FD-SOI CMOS

  • 期刊论文

  • 发表日期：

    2025年9月24日

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  • Yang Kuai,
  • Jiawen Wang,
  • Jiankang Li,
  • Feng Wang,
  • Liwei Yan,
  • Huanhuan He,
  • Fei Yang

摘要

This paper presents a 28–42 GHz digitally controlled variable-gain amplifier (VGA) with low phase variation for phased-array applications. Comparative analysis of traditional cascode current-canceling topologies reveals that the dominant contributors to phase errors are the drain–source parasitic capacitances (Cds) of common-gate transistors. To address this, a novel common-source current-canceling (CSCC) architecture incorporating a cross-connected transistor neutralization (CCTN) technique is proposed, effectively reducing phase error and enhancing isolation and stability. Furthermore, to simultaneously extend bandwidth and increase gain, the amplifier stage adopts a cascode configuration with an RCL feedback loop, combined with broadband transformer matching networks for wideband impedance transformation. The proposed VGA is fabricated in the 65-nm FD-SOI CMOS process, achieving a peak gain of 7 dB and a gain-control range (GCR) of 12 dB. Across the 3-dB bandwidth from 28 to 42 GHz, the phase variation is less than ± 5.6°, and the root-mean-square (RMS) phase error is 1.4°. The VGA core occupies 0.07 mm2 and consumes 21.8 mW from a 1.2 V supply.