CMOS Power Dividers and Variable-Gain Amplifier for 60 GHz Mobile Devices and 5G-Compatible Internet of Things (IoT)-Served Sensors
摘要
We demonstrate the design and analysis of three CMOS four-way power dividers and a CMOS variable-gain amplifier (VGA) for 60 GHz mobile devices and 5G-compatible internet-of-things (IoT)-served sensors. The first four-way power divider (PD1) constitutes three inverting single-spiral two-way power dividers. The second (PD2) and the third four-way power divider (PD3) constitute a dual-spiral two-way power divider followed by two inverting single-spiral two-way power dividers. Symmetrical and spiral transmission line (TL) with length of λ/9 is adopted to achieve miniature chip area and small amplitude imbalance (AI) and phase difference (PD). Remarkable results are achieved. For example, PD2 occupies a small chip area of 0.03 mm2, and achieves prominent S11 of -15.8, S23 of -29.9 dB, S21 of -8.327 dB, S31 of -8.472 dB, AI23 of 0.145 dB, and PD23 of 0.38° at 60 GHz. Moreover, the VGA constitutes a common-source (CS) input stage, followed by the current-reused CS first and second gain stages, and a cascode output stage. Bias current of the second gain stage (ID2) is reused by the first gain stage for power consumption (Pdc) reduction. Body node of the switch transistor M4 is connected to its gate via a large body floating resistance RB of 6.42 kΩ(i.e., DTMOS with RB topology) for S21 tuning range boosting of the VGA due to the reduction/increase of the on-state/off-state threshold voltage (Vth) of M4. The VGA consumes low power of 13.5 mW, and achieves excellent maximum S21 of 20.4 dB at 56.7 GHz, 3 dB gain bandwidth of 10 GHz (51.5–61.5 GHz), gain tuning range of 7.2 dB (from 20.4 dB to 13.2 dB), root-mean square (RMS) gain error of 0.38 dB, RMS phase error of 1.4°, output third-order intercept point (OIP3) of 16.7 dBm, and a figure-of-merit (FOM) of 34.65 GHz.