An engineering lot scheduling strategy for capacity ramp-up in real-world semiconductor manufacturing operations
摘要
Semiconductor manufacturing lines are constantly evolving, with new technologies and products being introduced at an accelerated pace in the market. In order to keep up with this rapid pace, it is essential to expedite the ramp-up of the production line, as delays can result in missed market opportunities and lost revenue. Expedited ramp-up requires careful planning and execution from recipe setup on the target machines to the final qualification for the mass production. Especially, scheduling engineering lots to collect data for the qualification process amid the current production schedule has been an important and difficult problem to resolve. However, it is currently managed mainly by the engineers’ experience and knowledge, which has led to variability and inefficiency in the ramp-up process. As a consequence, Samsung Electronics started to resolve this issue and introduced a systemized approach using a logic-based system and discrete-event simulation, which helps prioritize engineering lots in harmony with the current production schedule. In this work, we introduce the concept of our approach and show its performance through an actual field test.