Scholarlink

<p>In the realm of human–computer interaction, convolutional neural networks (CNN) have recently gained increasing attention for solving hand gesture recognition problems. Numerous existing CNN-based architectures perform well with recognition accuracy but may result in high computational complexity and require excessive resources when deployed on embedded devices. In this paper, an efficient hardware accelerator based on Tiny YOLOv2 networks using binary weights and low-bit activations is proposed to address the above issue. The processing elements (PEs) are designed to leverage low-bit calculations and resource allocation is employed to improve hardware performance. Furthermore, the design space of an accelerator is explored by fine-tuning parameters such as parallelization factors and clock rates. Experiments conducted on the PASCAL VOC and Hindi Indian Sign Language (ISL) datasets demonstrate that the Tiny YOLOv2 model with 1-bit weights and 5-bit activations achieves impressive mean average precision (mAP) scores of 50.2% and 59.4%, respectively. In addition, our accelerator design attains an inference latency of 33.3 ms with a high frame rate of 30 frames per second (FPS) for detecting gestures using the Xilinx ZCU104 FPGA. In terms of resource consumption and speed performance, our proposed design significantly performs better as compared to prior works.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

A low-bit quantized hardware accelerator for gesture classification and detection using deep learning algorithm

  • 期刊论文

  • 发表日期：

    2026年2月26日

查看全文
  • Mohita Jaiswal,
  • Abhishek Sharma,
  • Sandeep Saini

摘要

In the realm of human–computer interaction, convolutional neural networks (CNN) have recently gained increasing attention for solving hand gesture recognition problems. Numerous existing CNN-based architectures perform well with recognition accuracy but may result in high computational complexity and require excessive resources when deployed on embedded devices. In this paper, an efficient hardware accelerator based on Tiny YOLOv2 networks using binary weights and low-bit activations is proposed to address the above issue. The processing elements (PEs) are designed to leverage low-bit calculations and resource allocation is employed to improve hardware performance. Furthermore, the design space of an accelerator is explored by fine-tuning parameters such as parallelization factors and clock rates. Experiments conducted on the PASCAL VOC and Hindi Indian Sign Language (ISL) datasets demonstrate that the Tiny YOLOv2 model with 1-bit weights and 5-bit activations achieves impressive mean average precision (mAP) scores of 50.2% and 59.4%, respectively. In addition, our accelerator design attains an inference latency of 33.3 ms with a high frame rate of 30 frames per second (FPS) for detecting gestures using the Xilinx ZCU104 FPGA. In terms of resource consumption and speed performance, our proposed design significantly performs better as compared to prior works.