A variation-aware methodology for improved processor designs for the edge computing domain

Edge computing is increasingly important in the embedded domain as it improves latency, security, and energy efficiency. However, edge devices are often constrained by power budgets that limit achievable performance; thus improving energy efficiency is essential to achieve maximum performance under power constraints. An effective way of improving energy efficiency is the adoption microprocessors operating at Near-Threshold Voltage (NTV). Unfortunately, this comes with reduced frequency and increased process variations that must be harnessed. To address these challenges, we propose a two-step design methodology (design- and post-design time) for heterogeneous edge-based computing systems with NTV while effectively managing variations. Our methodology results in better-performing Multi-Processor Systems-on-Chip composed of a blend of cores at NTV or nominal voltages within a given power limit. Firstly, we propose a sampling-based methodology that enables variation-aware design exploration during the design stage. Secondly, we introduce an efficient post-design frequency scaling strategy to reduce power dissipation or improve system performance if possible. We evaluate our methodology using RISC-V heterogeneous cores and demonstrate that careful variation-aware design exploration can improve system performance by 52% on average compared to variation-unaware designs. Additionally, our methodology achieves a 12% improvement compared to variation-aware conventional designs that operate fully at nominal voltage.