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<p>Morphological operations such as dilation and erosion are the building blocks in today’s imaging processing streams for edge detection, denoising, and feature extraction. Still, conventional CMOS implementations suffer from inescapable area, power, and scalability limitations at nanoscale dimensions. This paper shows a compact Quantum-dot Cellular Automata (QCA) implementation that clearly overcomes these limitations in a three-layer design centered on two five-input majority gates. The design objective is to reduce interconnects, eliminate clock-zone crossings, and preserve a linear input–output interface that coincidentally maps naturally to sliding-window processing. The layout generated employs 38 QCA cells, occupies ≈ 0.04&#xa0;μm², and suffers 0.75 clock phases latency, achieving a deterministic sub-cycle timing profile that is suited for deterministic scheduling. Under a homogeneous evaluation process with standard QCA simulation software, the circuit demonstrates total energy dissipation of 1.19&#xa0;eV, within ≈ 2.6% of the optimal relative to the compared design. Hardware–software concordance is established by cross-verifying the hardware output against a Python implementation of dilation and erosion over sample binary and grayscale images and different kernel shapes and reporting 98.45–99.95% similarity across cases. Thermal robustness is evidenced by uniform mean output polarization over 1–8&#xa0;K, which deviates from the mean only slightly. Relative to the best alternatives considered, the solution circuit reduces up to 76.5% area, up to 68.3% fewer cells, and up to 25% less latency while retaining a uniform three-layer topology and simple I/O accessibility for tiling. Together, the above properties indicate that the design has a satisfactory compromise among density, speed, and energy and therefore is an effective QCA building block for nanoscale, energy-constrained, high-throughput image processing pipelines as well as a satisfactory basis for scalable compositions such as opening/closing phases or multi-stage morphological filters. The method also suggests a means of disciplined use of higher fan-in majority primitives to pack logic depth without losing routability, an idea that can be applied to proximal QCA imaging and signal-processing kernels.</p>

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A compact and efficient QCA-based nano-scale circuit for morphological operations in image processing

  • 期刊论文

  • 发表日期：

    2026年2月23日

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  • Saeid Seyedi,
  • Hatam Abdoli,
  • Mahnoush Sefidabian

摘要

Morphological operations such as dilation and erosion are the building blocks in today’s imaging processing streams for edge detection, denoising, and feature extraction. Still, conventional CMOS implementations suffer from inescapable area, power, and scalability limitations at nanoscale dimensions. This paper shows a compact Quantum-dot Cellular Automata (QCA) implementation that clearly overcomes these limitations in a three-layer design centered on two five-input majority gates. The design objective is to reduce interconnects, eliminate clock-zone crossings, and preserve a linear input–output interface that coincidentally maps naturally to sliding-window processing. The layout generated employs 38 QCA cells, occupies ≈ 0.04 μm², and suffers 0.75 clock phases latency, achieving a deterministic sub-cycle timing profile that is suited for deterministic scheduling. Under a homogeneous evaluation process with standard QCA simulation software, the circuit demonstrates total energy dissipation of 1.19 eV, within ≈ 2.6% of the optimal relative to the compared design. Hardware–software concordance is established by cross-verifying the hardware output against a Python implementation of dilation and erosion over sample binary and grayscale images and different kernel shapes and reporting 98.45–99.95% similarity across cases. Thermal robustness is evidenced by uniform mean output polarization over 1–8 K, which deviates from the mean only slightly. Relative to the best alternatives considered, the solution circuit reduces up to 76.5% area, up to 68.3% fewer cells, and up to 25% less latency while retaining a uniform three-layer topology and simple I/O accessibility for tiling. Together, the above properties indicate that the design has a satisfactory compromise among density, speed, and energy and therefore is an effective QCA building block for nanoscale, energy-constrained, high-throughput image processing pipelines as well as a satisfactory basis for scalable compositions such as opening/closing phases or multi-stage morphological filters. The method also suggests a means of disciplined use of higher fan-in majority primitives to pack logic depth without losing routability, an idea that can be applied to proximal QCA imaging and signal-processing kernels.