Optimizing a Mealy FSM Circuit in Mixed Element Basis

A method of reducing the number of LUT elements in the FPGA-based circuit of a Mealy finite state machine (FSM) is proposed. A part of the circuit is implemented using an embedded memory block (EMB). The method is based on the twofold state encoding, as well as encoding microoperation sets. An example of the FSM circuit synthesis using the proposed method is given. When certain conditions are met, there are exactly three levels of logic elements in an FSM circuit. Methods of improving circuit characteristics based on the optimal encoding of states and sets of microoperations are considered.