High-speed, low-power, and configurable on-chip training acceleration platform for spiking neural networks

Spike timing-dependent plasticity (STDP) is crucial for training neural networks (SNNs), offering a hardware-compatible and energy-efficient alternative to backpropagation. Current STDP hardware platforms encounter significant challenges, such as slowness, high energy consumption, and limited configurability. To overcome these issues, this paper presents a high-performance SNN training platform. A parallel multi-ring first-in-first-out structure with event-driven processing for spike handling is proposed, which enhances training efficiency, and the flexible pre- and post-synaptic parallelism enhances speed and flexibility. A dataflow strategy that considers spike sparsity unifies spike representations by updating weights only upon spike arrival, thereby promoting logical symmetry and enabling parallelization. Additionally, three encoding strategies, including a hybrid encoding, are implemented to address diverse scenarios. Leveraging Xilinx field-programmable gate array and Jetson Xavier NX, the proposed platform achieved remarkable performance gains. On the MNIST dataset, the platform demonstrated a 22.51 \(\times \) $\times$ speedup, 2.13% accuracy boost, and 14.79 \(\times \) $\times$ reduction in energy consumption. On the Fashion-MNIST dataset, it improved accuracy by 10.74% and the training speed by 1.89 \(\times \) $\times$ . Thus, this platform can significantly advance the SNN training efficiency and performance.