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<p>The persistent advancement of Very-Large-Scale Integration (VLSI) technology continues to place increasing demands on floorplanning techniques to achieve a maximum optimization of chip area, interconnect wirelength, and heat dissipations-destructive to performance, power consumption, and reliability. A classical optimization technique would face problems such as premature convergence, sub-optimal trade-offs, and scalability with respect to multi-objective scenarios. The aim of the study is to develop and characterize a novel hybrid metaheuristic framework, viz. ACSBO-QIFA, which integrates AC-SBO with QIFA. The ACSBO-QIFA approach used the chaotic dynamics for enhanced global exploration and the quantum-inspired mechanisms for accurate local refinement, providing a strong convergence behavior whisking-away from local optima. For evaluation, a dynamically weighted multi-objective fitness function was constructed with varying emphasis placed on area, wirelength, and thermal constraints, enabling flexible prioritization of design goals. The experimental verification conducted on MCNC benchmark circuits (apte, ami33, ami49, xerox, hp) proved its supremacy, even better than the latest methods. The new ACSBO-QIFA framework provides major advancements compared to existing solutions based on wirelength reductions (up to 3.60% on hp), lower temperatures (up to 3.92% on apte), and an overall area decrease of nearly 1.27% on xerox. On average for all the tests performed, the respective wirelengths were reduced by 1.82%, temperatures decreased by 2.34%, and the areas decreased by 0.47%. Collectively, these results demonstrate the excellent ability to optimize multiple objectives simultaneously. The demonstrated results add to the confidence in the ACSBO-QIFA for the generation of Pareto-optimal floorplanning, thus proposing it to be an efficient and high-scalable solution to challenges in modern VLSI design. The work creates the next roadmap for floorplanning tools to escort the balance between computational efficiency and constraints in varying semiconductor technologies.</p>

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A Convergence-driven metaheuristic framework for pareto-optimal VLSI floorplanning using ACSBO-QIFA

  • 期刊论文

  • 发表日期：

    2026年7月21日

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  • M. Prema,
  • T. Vaishnavi,
  • G. Merlin Suba,
  • Gunaselvi Manohar

摘要

The persistent advancement of Very-Large-Scale Integration (VLSI) technology continues to place increasing demands on floorplanning techniques to achieve a maximum optimization of chip area, interconnect wirelength, and heat dissipations-destructive to performance, power consumption, and reliability. A classical optimization technique would face problems such as premature convergence, sub-optimal trade-offs, and scalability with respect to multi-objective scenarios. The aim of the study is to develop and characterize a novel hybrid metaheuristic framework, viz. ACSBO-QIFA, which integrates AC-SBO with QIFA. The ACSBO-QIFA approach used the chaotic dynamics for enhanced global exploration and the quantum-inspired mechanisms for accurate local refinement, providing a strong convergence behavior whisking-away from local optima. For evaluation, a dynamically weighted multi-objective fitness function was constructed with varying emphasis placed on area, wirelength, and thermal constraints, enabling flexible prioritization of design goals. The experimental verification conducted on MCNC benchmark circuits (apte, ami33, ami49, xerox, hp) proved its supremacy, even better than the latest methods. The new ACSBO-QIFA framework provides major advancements compared to existing solutions based on wirelength reductions (up to 3.60% on hp), lower temperatures (up to 3.92% on apte), and an overall area decrease of nearly 1.27% on xerox. On average for all the tests performed, the respective wirelengths were reduced by 1.82%, temperatures decreased by 2.34%, and the areas decreased by 0.47%. Collectively, these results demonstrate the excellent ability to optimize multiple objectives simultaneously. The demonstrated results add to the confidence in the ACSBO-QIFA for the generation of Pareto-optimal floorplanning, thus proposing it to be an efficient and high-scalable solution to challenges in modern VLSI design. The work creates the next roadmap for floorplanning tools to escort the balance between computational efficiency and constraints in varying semiconductor technologies.