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<p>This research presents the design and implementation of a novel QuadCross Urdhva Tiryakbhyam (QCUT) Vedic multiplier utilizing the Urdhva Tiryakbhyam sutra to enhance the arithmetic computation efficiency. The proposed multiplier design integrates novel AND gates and hybrid half- and full-adder circuits. The novel multiplier circuit operates at high speed and relies significantly on the innovative 6&#xa0;T-AND gate circuits. The proposed 6&#xa0;T-AND gate circuit combines an inverter, a transmission gate, and a pull-down network using pass transistor logic to ensure error-free outputs. The proposed hybrid half-adder circuit uses an XOR-AND gate configuration to optimize the chip die area and reduce the average power consumption of these multiplier circuits. Specifically, the novel XOR circuit incorporates an inverter, a 2-to-1 mux, and pass transistor logic. The novel Vedic multiplier circuit integrates with hybrid full-swing adder (HFSA) circuits, which increase overall efficiency. Our innovative 4 × 4 QCUT Vedic multiplier demonstrated outperformance compared to its counterparts, achieving an average power of 103.64&#xa0;μW, remarkably low delays of 335.26&#xa0;ps, and a superior average PDP of 34.75 fJ. Using the Cadence Virtuoso software with GPDK 45&#xa0;nm technology within the ADEXL and LayoutXL design environment suites ensured the consistency of all circuits. This proposed method effectively combines the ancient Urdhva Tiryakbhyam (UT) sutra with the novel QuadCross technique to address contemporary problems in electronics and digital computing. It demonstrates the efficiency, scalability, and versatility of these proposed methods for the next-generation digital multipliers.</p>

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Design of a novel high-performance, energy-efficient, and area-optimized quadcross urdhva tiryakbhyam vedic multiplier

  • 期刊论文

  • 发表日期：

    2026年7月17日

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  • A. Arul,
  • M. Kathirvelu

摘要

This research presents the design and implementation of a novel QuadCross Urdhva Tiryakbhyam (QCUT) Vedic multiplier utilizing the Urdhva Tiryakbhyam sutra to enhance the arithmetic computation efficiency. The proposed multiplier design integrates novel AND gates and hybrid half- and full-adder circuits. The novel multiplier circuit operates at high speed and relies significantly on the innovative 6 T-AND gate circuits. The proposed 6 T-AND gate circuit combines an inverter, a transmission gate, and a pull-down network using pass transistor logic to ensure error-free outputs. The proposed hybrid half-adder circuit uses an XOR-AND gate configuration to optimize the chip die area and reduce the average power consumption of these multiplier circuits. Specifically, the novel XOR circuit incorporates an inverter, a 2-to-1 mux, and pass transistor logic. The novel Vedic multiplier circuit integrates with hybrid full-swing adder (HFSA) circuits, which increase overall efficiency. Our innovative 4 × 4 QCUT Vedic multiplier demonstrated outperformance compared to its counterparts, achieving an average power of 103.64 μW, remarkably low delays of 335.26 ps, and a superior average PDP of 34.75 fJ. Using the Cadence Virtuoso software with GPDK 45 nm technology within the ADEXL and LayoutXL design environment suites ensured the consistency of all circuits. This proposed method effectively combines the ancient Urdhva Tiryakbhyam (UT) sutra with the novel QuadCross technique to address contemporary problems in electronics and digital computing. It demonstrates the efficiency, scalability, and versatility of these proposed methods for the next-generation digital multipliers.