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<p>Quantum-dot Cellular Automata (QCA) offers a paradigm shift from conventional semiconductor technologies, leveraging quantum-mechanical tunneling and Coulomb interaction for ultra-low-power nanocomputing. This paper addresses the critical gap in QCA-based sequential circuits, particularly the absence of application-specific decimal systems, by proposing a novel D flip-flop and the first asynchronous Mod-10 BCD counter. The optimized D flip-flop utilizes only 21 cells, achieves a latency of 0.75 clock cycles, 33.3% faster than conventional designs, and exhibits the lowest reported energy dissipation. This robust D-FF enables a scalable BCD counter with integrated reset logic, designed using multilayer crossovers to ensure signal integrity and full input-output accessibility. The counter consumes 52.9% less energy than prior binary counters. It demonstrates exceptional thermal stability across the temperature range of 1–10&#xa0;K. These improvements in latency, energy efficiency, and functional completeness establish a new benchmark for QCA sequential design, paving the way for practical decimal applications, such as digital clocks and calculators, while providing a reliable foundation for future QCA-based nanoarchitectures.</p>

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A scalable asynchronous Mod-10 BCD counter realization using delay flip-flops: A quantum-dot cellular automata approach

  • 期刊论文

  • 发表日期：

    2026年6月30日

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  • Rohit Kumar Shaw,
  • Angshuman Khan,
  • Sudip Halder

摘要

Quantum-dot Cellular Automata (QCA) offers a paradigm shift from conventional semiconductor technologies, leveraging quantum-mechanical tunneling and Coulomb interaction for ultra-low-power nanocomputing. This paper addresses the critical gap in QCA-based sequential circuits, particularly the absence of application-specific decimal systems, by proposing a novel D flip-flop and the first asynchronous Mod-10 BCD counter. The optimized D flip-flop utilizes only 21 cells, achieves a latency of 0.75 clock cycles, 33.3% faster than conventional designs, and exhibits the lowest reported energy dissipation. This robust D-FF enables a scalable BCD counter with integrated reset logic, designed using multilayer crossovers to ensure signal integrity and full input-output accessibility. The counter consumes 52.9% less energy than prior binary counters. It demonstrates exceptional thermal stability across the temperature range of 1–10 K. These improvements in latency, energy efficiency, and functional completeness establish a new benchmark for QCA sequential design, paving the way for practical decimal applications, such as digital clocks and calculators, while providing a reliable foundation for future QCA-based nanoarchitectures.