<p>This work presents a reconfigurable analog logic architecture based on Cell Logic Analog Reconfigurable (CLAR) for the implementation of combinational logic and arithmetic functions. Each CLAR cell performs weighted summation and threshold-based operations using standard analog components, enabling the realization of Boolean logic functions through parameter reconfiguration. A systematic mapping between Boolean functions and analog weighted-sum structures is established, allowing the construction of higher-level building blocks such as adders, subtractors, comparators, and multiplexers. These elements are integrated into a one-bit analog arithmetic–logic unit (ALU), which is validated through simulation and proof-of-concept experimental observations. In addition to functional validation, the work includes an analysis of key performance aspects such as propagation delay, power consumption, and scalability. A comparison with digital, Field-Programmable Analog Arrays based, and emerging analog approaches highlights the trade-offs between flexibility, hardware efficiency, and implementation constraints. Although the proposed architecture is not intended to compete with highly integrated solutions in terms of area or power consumption, it provides a modular, transparent, and accessible platform for rapid prototyping, experimental research, and education in analog computation. The results demonstrate that CLAR-based systems constitute a viable and extensible approach for reconfigurable analog logic and arithmetic design, complementing conventional digital implementations.</p>