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<p>Polar codes have been the focus of increasing attention over the past ten years, and they have been selected as the control channel coding scheme in fifth-generation (5G) wireless communication systems. Because of its capacity-achieving property, multi-kernel (MK) polar codes are recommended as one of the most attractive channel codes to obtain more flexible block lengths. Polar codes have improved significantly over the last 10&#xa0;years in terms of power, decoding delay, complexity, and error-correction performance for finite-length codes under Field-Programmable Gate Array (FPGA) enabled belief propagation (BP) and successive cancellation (SC) algorithms. Nevertheless, the FPGA-enabled successive cancellation list (SCL) decoder is very large and has a long decoding latency. Therefore, based on the BPL decoding algorithm, a Belief Propagation List (BPL) decoder for MK polar codes is proposed in this research. Decoding makes use of multiple permuted factor graphs (PFGs) to further explore possible codewords. Finally, using Xilinx Verilog coding, the hardware architectures of the BPL decoder are executed in an FPGA. The result analysis shows that the proposed BPL decoder architecture accomplishes 250.64&#xa0;MHz maximum frequency, 3.02Gbps throughput, and consumes 0.922&#xa0;ns decoding delay for 1024-bit code length on the Virtex-7 FPGA platform.</p>

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FPGA enabled decoder design for multi-kernal polar codes in 5G communication

  • 期刊论文

  • 发表日期：

    2026年5月21日

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  • Moulana,
  • A. Niranjil Kumar

摘要

Polar codes have been the focus of increasing attention over the past ten years, and they have been selected as the control channel coding scheme in fifth-generation (5G) wireless communication systems. Because of its capacity-achieving property, multi-kernel (MK) polar codes are recommended as one of the most attractive channel codes to obtain more flexible block lengths. Polar codes have improved significantly over the last 10 years in terms of power, decoding delay, complexity, and error-correction performance for finite-length codes under Field-Programmable Gate Array (FPGA) enabled belief propagation (BP) and successive cancellation (SC) algorithms. Nevertheless, the FPGA-enabled successive cancellation list (SCL) decoder is very large and has a long decoding latency. Therefore, based on the BPL decoding algorithm, a Belief Propagation List (BPL) decoder for MK polar codes is proposed in this research. Decoding makes use of multiple permuted factor graphs (PFGs) to further explore possible codewords. Finally, using Xilinx Verilog coding, the hardware architectures of the BPL decoder are executed in an FPGA. The result analysis shows that the proposed BPL decoder architecture accomplishes 250.64 MHz maximum frequency, 3.02Gbps throughput, and consumes 0.922 ns decoding delay for 1024-bit code length on the Virtex-7 FPGA platform.