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<p>In this work, a three-stage Time-to-digital converter (TDC) based on the average measurement in the system is proposed for ranging. The ranging chip needs to provide 20&#xa0;MHz reference clock signal externally, which is doubled to 1&#xa0;GHz through the Phase-Locked Loop (PLL) circuit and sent to TDC to provide stable high frequency reference clock signal for the circuit. The circuit uses PLL cascaded oscillator units to generate multiple clock signals and vernier delay structures to construct two-stage interpolation. During the measurement process, the input signal is allocated to different channels of the TDC for multiple measurements and averaging. This not only reduces the random error caused by clock jitter due to noise, but also improves the utilization of TDC channels. The chip is based on X-Fab 0.18&#xa0;μm CMOS process, the core TDC layout area is 500&#xa0;μm × 350&#xa0;μm, the power consumption is about 16.55 mW, and the resolution is 14 ps. Analysis of the results of the post-simulation shows that the differential nonlinear peak is less than 0.4 LSB, and the integral nonlinear peak is less than 0.6 LSB. The dynamic range can increase the number of high-segment counter bits according to the needs of actual application scenarios. High measurement accuracy, linearity and wide dynamic range are achieved.</p>

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High precision time-to-digital converter chip design based on cycle and average logic

  • 期刊论文

  • 发表日期：

    2026年4月28日

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  • Kaizhuo Chen,
  • Zhiwei Huang,
  • Chongzhuo Zhao,
  • Chuanxin Teng,
  • Ming Chen,
  • Libo Yuan,
  • Shijie Deng

摘要

In this work, a three-stage Time-to-digital converter (TDC) based on the average measurement in the system is proposed for ranging. The ranging chip needs to provide 20 MHz reference clock signal externally, which is doubled to 1 GHz through the Phase-Locked Loop (PLL) circuit and sent to TDC to provide stable high frequency reference clock signal for the circuit. The circuit uses PLL cascaded oscillator units to generate multiple clock signals and vernier delay structures to construct two-stage interpolation. During the measurement process, the input signal is allocated to different channels of the TDC for multiple measurements and averaging. This not only reduces the random error caused by clock jitter due to noise, but also improves the utilization of TDC channels. The chip is based on X-Fab 0.18 μm CMOS process, the core TDC layout area is 500 μm × 350 μm, the power consumption is about 16.55 mW, and the resolution is 14 ps. Analysis of the results of the post-simulation shows that the differential nonlinear peak is less than 0.4 LSB, and the integral nonlinear peak is less than 0.6 LSB. The dynamic range can increase the number of high-segment counter bits according to the needs of actual application scenarios. High measurement accuracy, linearity and wide dynamic range are achieved.