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<p>Partially depleted silicon on Insulator ultra-thin body (PDSOI-UTB) FinFET based Capacitorless 1&#xa0;T-DRAM is designed and simulated. The PDSOI and UTB region of the proposed FinFET device is working as floating region and is utilised for storing holes for the application of Capacitorless 1&#xa0;T-DRAM. The holes are primarily generated by high-impact ionization occurring at the channel-drain junction. The PDSOI region is surrounded by low-k isolation dielectric oxide, which provides isolation between all the active regions. Hence, capacitive coupling between PDSOI region, gate, and UTB region is reduced. This increases the sensing margin of the device. The proposed device has several more advantages like low fabrication cost, low power consumption, very high sensing margin (~ 100 µA), retention time (&gt; 64&#xa0;ms) and high speed (~ 10&#xa0;ns) write and read operations.</p>

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Design of high performance capacitorless 1T-DRAM with PDSOI-UTB FinFET

  • 期刊论文

  • 发表日期：

    2026年5月6日

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  • Mitali Rathi,
  • Guru Prasad Mishra

摘要

Partially depleted silicon on Insulator ultra-thin body (PDSOI-UTB) FinFET based Capacitorless 1 T-DRAM is designed and simulated. The PDSOI and UTB region of the proposed FinFET device is working as floating region and is utilised for storing holes for the application of Capacitorless 1 T-DRAM. The holes are primarily generated by high-impact ionization occurring at the channel-drain junction. The PDSOI region is surrounded by low-k isolation dielectric oxide, which provides isolation between all the active regions. Hence, capacitive coupling between PDSOI region, gate, and UTB region is reduced. This increases the sensing margin of the device. The proposed device has several more advantages like low fabrication cost, low power consumption, very high sensing margin (~ 100 µA), retention time (> 64 ms) and high speed (~ 10 ns) write and read operations.