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<p>In Very Large Scale Integrated Circuits, the Built in Self-Test (BIST) is intended to minimize power consumption while providing fault coverage. Weighted pseudorandom (W-Pr) BIST mechanism is employed to minimize the several vectors requirement for attaining entire fault coverage. The weights 0, 0.5 and 1 are included in the weight sets so far to create test patterns for reducing the duration of testing and amount of energy consumed. LP-LFSRs, or Low Power Linear Feedback Shift Registers, are used in this study for creating test patterns. A single input change (SIC) pattern is created when seeds from an LP-LFSR are Exclusive ORed with a Grey code (GC) generator and counter. The inclusion of accumulators, which are widely found in current VLSI chips, effectively lowers the amount of hardware needed for the production of BIST patterns when using this technique. Modelism 6.4c is used to validate the suggested technique and Verilog HDL is used to simulate it. The simulation results exhibit that the power consumed for testing utilizing the recommended architecture is significantly decreased.</p>

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Power-aware test pattern generation with LP-LFSRs and counter-assisted gray code for VLSI BIST

  • 期刊论文

  • 发表日期：

    2026年5月2日

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  • C. Thangam,
  • R. Manjith

摘要

In Very Large Scale Integrated Circuits, the Built in Self-Test (BIST) is intended to minimize power consumption while providing fault coverage. Weighted pseudorandom (W-Pr) BIST mechanism is employed to minimize the several vectors requirement for attaining entire fault coverage. The weights 0, 0.5 and 1 are included in the weight sets so far to create test patterns for reducing the duration of testing and amount of energy consumed. LP-LFSRs, or Low Power Linear Feedback Shift Registers, are used in this study for creating test patterns. A single input change (SIC) pattern is created when seeds from an LP-LFSR are Exclusive ORed with a Grey code (GC) generator and counter. The inclusion of accumulators, which are widely found in current VLSI chips, effectively lowers the amount of hardware needed for the production of BIST patterns when using this technique. Modelism 6.4c is used to validate the suggested technique and Verilog HDL is used to simulate it. The simulation results exhibit that the power consumed for testing utilizing the recommended architecture is significantly decreased.