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<p>This article represents an 8-bit 1 MS/s Low-Power Successive Approximation Register Analog-to-Digital Converter (SAR ADC) incorporating a randomized Dynamic Element Matching (DEM) 8 × 8 Capacitive Digital-to-Analog-Converter (CDAC) and an enhanced Edge Pursuit Comparator (EPC). It is designed and simulated in Cadence Virtuoso 180&#xa0;nm UMC Complementary Metal Oxide Semiconductor (CMOS) technology, operating at a supply voltage of 1.8&#xa0;V and a sampling frequency of 1 MS/s. From the post-layout simulation results, it is found that the proposed 8-bit SAR ADC consumes a power of about 73.34 µW at 1 MS/s sampling rate. It achieves a Differential Non Linearity (DNL) of 0.99 LSB, an Integral Non Linearity (INL) of 1.4 LSB in post layout simulation. The proposed ADC shows a post layout simulated dynamic performance characteristics with a Signal to Noise Distortion Ratio (SNDR) of 49.53 dB, a Spurious Free Dynamic Range (SFDR) of 62.96 dB, and an Effective Number of Bits (ENoB) of 7.934 bits, respectively, for a 50.781&#xa0;kHz input signal. Moreover, Monte Carlo simulations are performed, and dynamic performance characteristics are examined for different input frequencies with satisfactory performance. The proposed ADC occupies an active area of 0.0338 sq.mm.</p>

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An 8-bit 1 MS/s low-power SAR ADC realized with an enhanced EPC and a randomized DEM 8 × 8 CDAC

  • 期刊论文

  • 发表日期：

    2026年2月20日

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  • Deepika Kumaradasan,
  • Santanu Sarkar,
  • Sougata Kumar Kar

摘要

This article represents an 8-bit 1 MS/s Low-Power Successive Approximation Register Analog-to-Digital Converter (SAR ADC) incorporating a randomized Dynamic Element Matching (DEM) 8 × 8 Capacitive Digital-to-Analog-Converter (CDAC) and an enhanced Edge Pursuit Comparator (EPC). It is designed and simulated in Cadence Virtuoso 180 nm UMC Complementary Metal Oxide Semiconductor (CMOS) technology, operating at a supply voltage of 1.8 V and a sampling frequency of 1 MS/s. From the post-layout simulation results, it is found that the proposed 8-bit SAR ADC consumes a power of about 73.34 µW at 1 MS/s sampling rate. It achieves a Differential Non Linearity (DNL) of 0.99 LSB, an Integral Non Linearity (INL) of 1.4 LSB in post layout simulation. The proposed ADC shows a post layout simulated dynamic performance characteristics with a Signal to Noise Distortion Ratio (SNDR) of 49.53 dB, a Spurious Free Dynamic Range (SFDR) of 62.96 dB, and an Effective Number of Bits (ENoB) of 7.934 bits, respectively, for a 50.781 kHz input signal. Moreover, Monte Carlo simulations are performed, and dynamic performance characteristics are examined for different input frequencies with satisfactory performance. The proposed ADC occupies an active area of 0.0338 sq.mm.