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<p>This work presents the design and implementation of a Low Noise Amplifier (LNA) incorporating a variable gain amplifier to adjust gain according to input signal strength. The realized LNA employs a dual feedback resistance configuration to enhance impedance matching and improve circuit stability. The pre layout simulation results depict the maximum gain of 13.5 dB at 1.67&#xa0;GHz under high transconductance conditions while for low transconductance conditions, the circuit provides a maximum gain of 12.18 dB at 1.67&#xa0;GHz, demonstrating effective variable gain control through the ON/OFF switching of MOS transistor M<sub>4</sub>. The input reflection coefficient (S<sub>11</sub>) is less than − 9 dB across the 1.5–2.0&#xa0;GHz frequency range while reverse isolation (S<sub>12</sub>) remains below − 10 dB throughout the band. The minimum noise figure (NF) achieved is 1.4 dB in the MOS M<sub>4</sub> OFF state and 1.53 dB in the M<sub>4</sub> ON state. The post layout results illustrate the maximum value of S<sub>21</sub> is 12.52 dB for the high transconductance and 11.2 dB for the low transconductance. S<sub>11</sub> value is – 19.6 dB for MOS M<sub>4</sub> OFF state and − 16.2 dB for MOS M4 ON state. NF is 1.60 dB for MOS M<sub>4</sub> OFF condition and 1.76 dB for MOS M<sub>4</sub> ON condition. The power consumption of the realized circuit is 114.8 mW using 1.8&#xa0;V supply. The layout area of the realized circuit is 0.0499 mm<sup>2</sup>.</p>

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Low noise figure LNA using noise cancellation and variable gain amplifier

  • 期刊论文

  • 发表日期：

    2026年2月17日

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  • Dheeraj Kalra,
  • Manish Kumar

摘要

This work presents the design and implementation of a Low Noise Amplifier (LNA) incorporating a variable gain amplifier to adjust gain according to input signal strength. The realized LNA employs a dual feedback resistance configuration to enhance impedance matching and improve circuit stability. The pre layout simulation results depict the maximum gain of 13.5 dB at 1.67 GHz under high transconductance conditions while for low transconductance conditions, the circuit provides a maximum gain of 12.18 dB at 1.67 GHz, demonstrating effective variable gain control through the ON/OFF switching of MOS transistor M4. The input reflection coefficient (S11) is less than − 9 dB across the 1.5–2.0 GHz frequency range while reverse isolation (S12) remains below − 10 dB throughout the band. The minimum noise figure (NF) achieved is 1.4 dB in the MOS M4 OFF state and 1.53 dB in the M4 ON state. The post layout results illustrate the maximum value of S21 is 12.52 dB for the high transconductance and 11.2 dB for the low transconductance. S11 value is – 19.6 dB for MOS M4 OFF state and − 16.2 dB for MOS M4 ON state. NF is 1.60 dB for MOS M4 OFF condition and 1.76 dB for MOS M4 ON condition. The power consumption of the realized circuit is 114.8 mW using 1.8 V supply. The layout area of the realized circuit is 0.0499 mm2.