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<p>In digital signal processing (DSP), the squaring operation is required for several crucial processes such as discrete Fourier transform, convolution and digital filters. In literature, the squarer is implemented using traditional multipliers. This architecture requires a larger number of gates, which increases area and power consumption. In order to address the current problems, this paper introduces a self-multiplier design using quantum dot cellular automata (QCA). The proposed 2-bit square circuit (P2BSC) and the proposed 4-bit square circuit (P4BSC) are implemented with the help of an inverter gate (INV), a 3 input majority voter gate (MV3), a 5 input majority voter gate (MV5) and an XOR gate with 2 inputs. The 2-bit square architecture has 24 cells, which is 62.5% less than the number of cells in the existing versions. A circuit delay of 0.5 clock cycles (CLKS) and a footprint of 0.03 <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\mu {{m}^{2}}\)</EquationSource> </InlineEquation>, which is 62.5% less than that of the existing design observed. The 4-bit squarer circuit is built with 450 cells only, which is 35.1% less than the design found in the literature. It has a delay of 2.5 CLKS and an area of 0.68 <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(\mu {{m}^{2}}\)</EquationSource> </InlineEquation>, which is 16% less than that of the existing designs. This circuit design incorporates clock zone-based crossovers (CZBCO). The QCADesigner and QCADesigner-E software packages were used for performance analyses.</p>

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Efficient architecture for square circuit using Quantum Dot Cellular Automata (QCA)

  • 期刊论文

  • 发表日期：

    2026年2月20日

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  • Yovan Snanagan Ponselvan Devasahayam,
  • Nakkeeran Rangaswamy

摘要

In digital signal processing (DSP), the squaring operation is required for several crucial processes such as discrete Fourier transform, convolution and digital filters. In literature, the squarer is implemented using traditional multipliers. This architecture requires a larger number of gates, which increases area and power consumption. In order to address the current problems, this paper introduces a self-multiplier design using quantum dot cellular automata (QCA). The proposed 2-bit square circuit (P2BSC) and the proposed 4-bit square circuit (P4BSC) are implemented with the help of an inverter gate (INV), a 3 input majority voter gate (MV3), a 5 input majority voter gate (MV5) and an XOR gate with 2 inputs. The 2-bit square architecture has 24 cells, which is 62.5% less than the number of cells in the existing versions. A circuit delay of 0.5 clock cycles (CLKS) and a footprint of 0.03 \(\mu {{m}^{2}}\) , which is 62.5% less than that of the existing design observed. The 4-bit squarer circuit is built with 450 cells only, which is 35.1% less than the design found in the literature. It has a delay of 2.5 CLKS and an area of 0.68 \(\mu {{m}^{2}}\) , which is 16% less than that of the existing designs. This circuit design incorporates clock zone-based crossovers (CZBCO). The QCADesigner and QCADesigner-E software packages were used for performance analyses.