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<p>Several studies have shown the benefits of Machine Learning (ML) approaches for automating and improving Integrated Circuit (IC) layout processes both digital and analog. However, the challenge of data scarcity persists in electronic design, particularly when aiming to train highly accurate ML models. This paper proposes a method for enhancing VLSI circuit performance prediction through Qualitative Data Augmentation using Mixed-Decomposed Convolutional Network (VLSI-QDA-MDCN). Here, the data is collected from EDA technologies like, HSpice, Micro-Cap and Cadence Virtuoso including fourteen delay datasets derived from basic digital circuits and six frequently used analog electronic devices. The process and design factors that differentiate the training data for a given circuit topology create. However, privacy concerns and other constraints limit this data collection technique. To address these limitations, the Qualitative Data Augmentation (QDA) is performed using Mixed-Decomposed Convolutional Network (MDCN), which contributes to the enhancement of the precision of machine learning models trained on a limited dataset. The training data is obtained by simulations using 22&#xa0;nm and 180&#xa0;nm CMOS technology nodes from TSMC in Cadence Virtuoso, HSPICE, Microcap design environments. The proposed VLSI-QDA-MDCN method is implemented in Python. The proposed method achieves 23.62%, 25.96%, 26.23% low MSE; 34.83%, 33.02% and 25.98% low RMSE when compared with existing techniques, like QDA-VLSI-GAN, GNN-VLSI-DAT and ADED-VLSI-MMD.</p>

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Enhancing VLSI circuit performance prediction through qualitative data augmentation using Mixed-decomposed convolutional network

  • 期刊论文

  • 发表日期：

    2026年1月16日

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  • S. Nagarajan,
  • J. Jeba Johannah,
  • E. Malarvizhi,
  • S. Lakshmi

摘要

Several studies have shown the benefits of Machine Learning (ML) approaches for automating and improving Integrated Circuit (IC) layout processes both digital and analog. However, the challenge of data scarcity persists in electronic design, particularly when aiming to train highly accurate ML models. This paper proposes a method for enhancing VLSI circuit performance prediction through Qualitative Data Augmentation using Mixed-Decomposed Convolutional Network (VLSI-QDA-MDCN). Here, the data is collected from EDA technologies like, HSpice, Micro-Cap and Cadence Virtuoso including fourteen delay datasets derived from basic digital circuits and six frequently used analog electronic devices. The process and design factors that differentiate the training data for a given circuit topology create. However, privacy concerns and other constraints limit this data collection technique. To address these limitations, the Qualitative Data Augmentation (QDA) is performed using Mixed-Decomposed Convolutional Network (MDCN), which contributes to the enhancement of the precision of machine learning models trained on a limited dataset. The training data is obtained by simulations using 22 nm and 180 nm CMOS technology nodes from TSMC in Cadence Virtuoso, HSPICE, Microcap design environments. The proposed VLSI-QDA-MDCN method is implemented in Python. The proposed method achieves 23.62%, 25.96%, 26.23% low MSE; 34.83%, 33.02% and 25.98% low RMSE when compared with existing techniques, like QDA-VLSI-GAN, GNN-VLSI-DAT and ADED-VLSI-MMD.