This work proposes a Phase Frequency Detector (PFD) based on Dynamic Pass Transistor Logic (DPTL). Since the circuit is designed without a reset-path, the dead zone and blind zone are effectively eliminated. Due to the elimination of dead and blind zones, the \(\phi\) -V characteristics of the PFD exhibit enhanced linearity over the range from – \(\pi\) to \(\pi\) . To optimize the PFD, Taguchi and ANOVA statistical approaches were applied. The optimized PFD operates at a maximum-frequency of 9.1 GHz with a delay of 53.86 ps, while consuming 5.17 \(\mu\) W of power and exhibiting a phase-noise of –156.099 dBc/Hz. Based on the proposed PFD, a GHz-range synthesizer was implemented, exhibiting a power dissipation of 7.85 mW at 1.8 V, a lock-time of 0.23 \(\mu\) s, and a frequency tuning range of 0.5–10.44 GHz, while having an area of 0.017 mm2. The robustness of the PFD and frequency synthesizer circuits was evaluated under process, voltage, and temperature (PVT) variations for both pre- and post-layout simulations. With its wide tuning range, the proposed frequency synthesizer is well-suited for wireless communication, satellite links, radar systems, and GPS navigation.
