This work introduces a novel quadruple-channel FinFET design to address the limitations of conventional MOSFETs, particularly short-channel effects. Significant performance enhancements have been achieved through rigorous optimization of key parameters such as fin width, threshold voltage ( \(V_{th}\) ), Drain-Induced Barrier Lowering (DIBL), and drain current ( \(I_D\) ). For 5nm fin width, the optimized structure exhibits a low \(V_{th}\) of 0.31V, a minimal DIBL of 22mV/V, and a high normalized drain current of 820 \(\mu\) A/ \(\mu\) m. The 5nm structure also shown excellent transconductance of 2720 \(\mu\) S/ \(\mu\) m. The parameters obtained for 5nm show significantly improved performance as compared to Bulk-MOSFET. Furthermore, for 20nm fin width, the optimized design demonstrates a \(V_{th}\) of 0.247V and a drain current of 148 \(\mu\) A at a gate voltage of 0.7V. Importantly, the quadruple-channel FinFET exhibits a significantly improved \(\hbox {I}_{ON}\) / \(\hbox {I}_{OFF}\) ratio ( \(29.6 \times 10^5\) for 5 nm fin width) and a reduced subthreshold swing (109mV/decade for 5nm fin width). These results indicate enhanced scalability and reduced leakage currents, even at smaller device dimensions, demonstrating a clear performance advantage over conventional FinFET structures. By investigating the circuit performance, the designed FET exhibits a sharp transition in its inverting behavior, a desirable characteristic for digital circuit applications. A peak gain was observed at a 5nm fin width. Transient analysis demonstrates the designed structure’s low rise and fall times, confirming its suitability for high-speed and precision applications. Specifically, for the 20nm Fin-width, a minimum rise time of 15ps and a fall time of 10ps were observed.
