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<p>Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs), because of its scalability and efficiency. Congestion is one of the main issues with the NoC, which results in delays and lowers the architecture’s overall performance. In order to prevent congestion and improve the NoC’s latency and power performance, an Improved Congestion Aware Virtual Channel Router (ICAwVCR) has been developed in this study. The Buffer Utilization Rate credit controller (BURCC), which is also used to alter XY dimension routing in ICAwVCR, assists in detecting congestion at the router. Similarly, fine-grained power gating techniques are used to achieve static power savings during routing. Furthermore, the packet loss is avoided by adapting the 2nd order delta run length encoding based packet compression framework (∆RL-Zip) in the Network Interface (NI), which compresses/decompresses the data into/from the underlying interconnection network. The proposed routing algorithm is executed on a 4 × 4 mesh NoC using Xilinx FPGA design with Verilog coding. The proposed router accomplishes a 0.92% compression ratio (CR) and consumes 7.1mW power consumption, which is considerably better than the existing routing algorithms.</p>

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Design of low-power network on-chip using an improved congestion-aware virtual channel router with power gating mechanism

  • 期刊论文

  • 发表日期：

    2025年10月22日

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  • P. Sivagamasundhari,
  • M. Santhi

摘要

Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs), because of its scalability and efficiency. Congestion is one of the main issues with the NoC, which results in delays and lowers the architecture’s overall performance. In order to prevent congestion and improve the NoC’s latency and power performance, an Improved Congestion Aware Virtual Channel Router (ICAwVCR) has been developed in this study. The Buffer Utilization Rate credit controller (BURCC), which is also used to alter XY dimension routing in ICAwVCR, assists in detecting congestion at the router. Similarly, fine-grained power gating techniques are used to achieve static power savings during routing. Furthermore, the packet loss is avoided by adapting the 2nd order delta run length encoding based packet compression framework (∆RL-Zip) in the Network Interface (NI), which compresses/decompresses the data into/from the underlying interconnection network. The proposed routing algorithm is executed on a 4 × 4 mesh NoC using Xilinx FPGA design with Verilog coding. The proposed router accomplishes a 0.92% compression ratio (CR) and consumes 7.1mW power consumption, which is considerably better than the existing routing algorithms.