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<p>This paper proposes an efficient Finite Impulse Response (FIR) filter design using a novel pruning technique optimized with the Secretary Bird Optimization (SBO) algorithm. The key novelty lies in the introduction of a customized multi-objective cost function that integrates coefficient significance, power consumption, delay, and area, enabling hardware-aware pruning decisions. Unlike standard SBO applications, the algorithm is adapted for FIR filter design by dynamically balancing exploration and exploitation phases through a feedback coefficient mechanism. The proposed method effectively identifies and eliminates less significant filter components to reduce complexity without compromising performance. Implementation results demonstrate substantial improvements: up to 30.5% reduction in power, 35% reduction in delay, 21.1% decrease in area, and up to 63.4% reduction in area-delay product across different filter tap sizes. These results validate the proposed approach as a scalable and energy-efficient solution for digital signal processing applications, particularly suitable for low-power VLSI systems.</p>

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Low-Power FIR filter pruning using secretary bird optimization for Hardware-Efficient signal processing

  • 期刊论文

  • 发表日期：

    2025年9月5日

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  • G. Theivanathan,
  • C. Murukesh

摘要

This paper proposes an efficient Finite Impulse Response (FIR) filter design using a novel pruning technique optimized with the Secretary Bird Optimization (SBO) algorithm. The key novelty lies in the introduction of a customized multi-objective cost function that integrates coefficient significance, power consumption, delay, and area, enabling hardware-aware pruning decisions. Unlike standard SBO applications, the algorithm is adapted for FIR filter design by dynamically balancing exploration and exploitation phases through a feedback coefficient mechanism. The proposed method effectively identifies and eliminates less significant filter components to reduce complexity without compromising performance. Implementation results demonstrate substantial improvements: up to 30.5% reduction in power, 35% reduction in delay, 21.1% decrease in area, and up to 63.4% reduction in area-delay product across different filter tap sizes. These results validate the proposed approach as a scalable and energy-efficient solution for digital signal processing applications, particularly suitable for low-power VLSI systems.