In the age of fast digital communication, the use of portable devices is significantly increasing. Given their compact size, it is essential for these devices to fulfill the technological requirements of reduced power consumption, minimal area, and high speed. The 1-bit full adder cell is a critical functional unit in the computational industry. This paper presents a new hybrid methodology for designing 20 transistor full adder (FA) based on Double Gate MOSFET (20T-HyDGFA). The proposed circuit is designed to optimize the balance between propagation delay (Td) and power consumption (PWR), therefore enhancing efficiency in the IC sector. This study compares the proposed circuit with existing FA circuits and measures numerous performance metrics, including Td, PWR, Power Delay Product (PDP), Energy Delay Product (EDP), Energy-Delay² Product (ED2P), and noise margin. Operated at a supply voltage (VDD) of 0.5 V, the proposed design exhibits a notably low PWR of 0.98nW (1.18x), with a remarkably short Td of 19.30ps (20.63x), accompanied by a substantial PDP of 0.02 aJ (24.22x), EDP of 0.36 aJ-ns (500.22x) and ED2P of 6.21 aJ-ps2 (1150x) as simulated on HSPICE software at a 16 nm technology node. A detailed, Monte Carlo Simulation is conducted for the proposed FA circuit to validate the obtained results and then compared with the existing best state-of-the-art FA circuits. Furthermore, this paper introduces an application, 4-Bit Ripple Carry Adder (RCA), using the proposed 20T-HyDGFA Circuit (4-HyDGRCA). The physical layout design is facilitated by the enhanced results, which occupy an optimized area of 9.3µm2 and 41.9 µm2 for the proposed circuit and proposed application circuit, respectively.
