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<p>The primary objective of the work is to demonstrate the efficacy of a recently proposed adiabatic logic family called improved Diode-Free Adiabatic Logic (IDFAL), particularly for sequential circuit applications under variable conditions. The IDFAL architecture employs a two-phase clocking mechanism along with a complementary split-level sinusoidal power supply for efficient energy recovery. Extensive simulations were conducted on various sequential circuits using IDFAL at 45&#xa0;nm technology node, employing Berkeley Low Power Predictive Technology Model (LP PTM V2.1). Since adiabatic logic is efficient at lower operating frequencies, analyses were performed at 100&#xa0;kHz and 400&#xa0;kHz. The study was carried out using Cadence Virtuoso in an analog environment with Spectre<Emphasis Type="BoldItalic">®</Emphasis>. The performance of IDFAL-based sequential circuits is compared against conventional CMOS and other recent adiabatic logic styles, including Clocked CMOS Adiabatic Logic (CCAL), 2PASCL, 2PADCL, ADCL, DFAL, and QSERL. Power efficiency remains a critical factor for high-performance, portable applications. Energy recovery techniques based on adiabatic switching help reduce power by conserving energy stored in load capacitors. IDFAL, based on CMOS principles, incorporates a sinusoidal power clock and additional control transistors to lower peak currents and leakage power. Simulation results indicate that IDFAL achieves the lowest Power Delay Product (PDP) and Energy Delay Product (EDP) among the predictable designs.</p>

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Architectural design of sequential circuit based on improved diode-free adiabatic logic

  • 期刊论文

  • 发表日期：

    2025年8月15日

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  • Reginald H. Vanlalchaka,
  • Reshmi Maity,
  • Ricky L. Ralte,
  • L. R. M. Punte,
  • P. C. Rohmingliana,
  • R. Lalawmpuii,
  • Niladri Pratap Maity

摘要

The primary objective of the work is to demonstrate the efficacy of a recently proposed adiabatic logic family called improved Diode-Free Adiabatic Logic (IDFAL), particularly for sequential circuit applications under variable conditions. The IDFAL architecture employs a two-phase clocking mechanism along with a complementary split-level sinusoidal power supply for efficient energy recovery. Extensive simulations were conducted on various sequential circuits using IDFAL at 45 nm technology node, employing Berkeley Low Power Predictive Technology Model (LP PTM V2.1). Since adiabatic logic is efficient at lower operating frequencies, analyses were performed at 100 kHz and 400 kHz. The study was carried out using Cadence Virtuoso in an analog environment with Spectre®. The performance of IDFAL-based sequential circuits is compared against conventional CMOS and other recent adiabatic logic styles, including Clocked CMOS Adiabatic Logic (CCAL), 2PASCL, 2PADCL, ADCL, DFAL, and QSERL. Power efficiency remains a critical factor for high-performance, portable applications. Energy recovery techniques based on adiabatic switching help reduce power by conserving energy stored in load capacitors. IDFAL, based on CMOS principles, incorporates a sinusoidal power clock and additional control transistors to lower peak currents and leakage power. Simulation results indicate that IDFAL achieves the lowest Power Delay Product (PDP) and Energy Delay Product (EDP) among the predictable designs.